Patent application number | Description | Published |
20140084470 | Seed Layer Structure and Method - A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness. | 03-27-2014 |
20140117547 | BARRIER LAYER FOR COPPER INTERCONNECT - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer. | 05-01-2014 |
20140191402 | Barrier Layer for Copper Interconnect - A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 07-10-2014 |
20150044867 | Barrier Layer for Copper Interconnect - A device and a method of forming the device is provided. The device includes a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 02-12-2015 |
Patent application number | Description | Published |
20120314989 | OPTICAL TRANSCEIVER MODULE - An optical transceiver module includes a circuit board, at least two optical sub-assemblies, and an interface. The optical sub-assembly electrically connects with the circuit board and includes an optoelectronic component and an integrally-formed optical fiber. The interface electrically connects with the circuit board including a plurality of pins penetrating through the circuit board. | 12-13-2012 |
20130064498 | OPTICAL SUB-ASSEMBLY MODULE AND INTERMEDIATE OPTICAL MECHANISM - An optical sub-assembly module comprises a fiber for delivering optical signals; a transmitter; a receiver; and an intermediate optical mechanism optically coupled to the fiber, the transmitter and the receiver. The intermediate optical mechanism includes a fiber-end interface for receiving the optical signals from the fiber or outputting the optical signals generated by the transmitter to the fiber; a transmission-end interface for receiving the optical signals from the transmitter; a reception-end interface or outputting the optical signals from the fiber to the receiver; and a filtering interface in the inside of the intermediate optical mechanism for realizing the optical signal delivery from the transmitter to the fiber and from the fiber to the receiver. The fiber-end interface, the transmission-end interface and the reception-end interface are parts of an integral whole while the filtering interface is a part of the same integral whole or an independent filter. | 03-14-2013 |
20130156417 | OPTICAL FIBER TRANSMISSION SWITCHING DEVICE AND CONTROL METHOD THEREOF - An optical fiber transmission switching device includes a first transmission port; a second transmission port; a terminal-end input port; a terminal-end output port; a first and a second optical module respectively including an electrical input port, an electrical output port, and a bi-directional optical port, wherein the two bi-directional optical ports are coupled to the first and the second transmission port respectively; a first and a second laser driver circuit respectively coupled to the first and the second optical module; a first and a second electrical amplifier respectively coupled to the first and the second optical module; a first switching module coupled to the terminal-end input port and the first and the second laser driver circuit; a second switching module coupled to the first and the second electrical amplifier and the terminal-end output port. | 06-20-2013 |
Patent application number | Description | Published |
20130285190 | Layout of a MOS Array Edge with Density Gradient Smoothing - A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry. | 10-31-2013 |
20140040836 | GRADED DUMMY INSERTION - Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example. | 02-06-2014 |
20140042585 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device. | 02-13-2014 |
20140110787 | Layout Schemes for Cascade MOS Transistors - A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected. | 04-24-2014 |
20140159932 | ARRANGEMENT FOR DIGITAL-TO-ANALOG CONVERTER - Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout. | 06-12-2014 |
20140245242 | VARIATION FACTOR ASSIGNMENT - One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments. | 08-28-2014 |
20150362539 | OUTPUT RESISTANCE TESTING STRUCTURE AND METHOD OF USING THE SAME - A testing structure includes a first transistor having a first dopant type connected to a current source. The testing structure further includes a second transistor having a second dopant type, opposite to the first dopant type. The second transistor is connected to a device under test (DUT). The second transistor is connected in series with the first transistor in a cascode arrangement. The cascode arrangement is capable of measuring an output resistance of the DUT of greater than 1 mega-ohm (MΩ). | 12-17-2015 |
20150362540 | CIRCUIT AND METHOD FOR GAIN MEASUREMENT - A circuit for measuring a gain of an amplifier includes a first node coupled to an output of the amplifier, a second node, a first circuit coupled to an input and the output of the amplifier, and a second circuit coupled between the first circuit and the second node. The first circuit is configured to cause a first gain drop in a gain to be measured between the first node and the second node. The second circuit configured to cause a second gain drop in the gain to be measured between the first node and the second node. | 12-17-2015 |
20150362541 | CIRCUIT AND METHOD FOR BANDWIDTH MEASUREMENT - A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier. | 12-17-2015 |
20150370946 | METHOD OF DENSITY-CONTROLLED FLOORPLAN DESIGN FOR INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS - A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule. | 12-24-2015 |
20150379174 | VARIATION MODELING - A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout. | 12-31-2015 |
20160035715 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other. | 02-04-2016 |