Patent application number | Description | Published |
20110164006 | DISPLAY DRIVE CIRCUIT - A display driving circuit includes a buffer section, an N-dot switch circuit, a charge sharing switch circuit, and a sharing voltage level control switch circuit. The buffer section buffers a plurality of pixel driving signals outputted from a plurality of DACs. The N-dot switch circuit selects paths of the plurality of pixel driving signals outputted from the buffer section in response to a first path selecting signal or a second path selecting signal that is determined depending upon a dot inversion method, and switches the paths to a plurality of output terminals. The charge sharing switch circuit shares charges among the plurality of output terminals in response to a charge sharing control signal. The sharing voltage level control switch circuit controls charge sharing between the plurality of output terminals and a voltage level upon charge sharing, in response to a sharing voltage level control signal. | 07-07-2011 |
20110164020 | DISPLAY DRIVE CIRCUIT AND DRIVE METHOD - A display driving circuit and method is capable of minimizing the residual image of a display panel as well as consumption electric current. The display driving circuit generates driving signals corresponding to valid data and black data and transmits the driving signals to a display panel, and includes N data selection switches (where N is the integer), N buffers, N buffer output selection switches, and multiple charge sharing switches. The N data selection switches select one of the valid data and the black data. The N buffers buffer the signal selected by the respective data selection switches. The N buffer output selection switches switch outputs of the buffers to output the respective driving signals. The multiple charge sharing switches connect the neighboring pairs of the driving signals. | 07-07-2011 |
20110169808 | AMPLIFIER INCLUDING DITHERING SWITCH AND DISPLAY DRIVING CIRCUIT USING THE AMPLIFIER - An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other. | 07-14-2011 |
20110199821 | POWER MANAGEMENT CHIP FURNISHED WITH VOLTAGE CONTROLLER - A power management IC includes a first IC having a boost converter IC which generates a second voltage using a first voltage supplied from an outside and supplies the second voltages to a charge pump, a reference voltage generation circuit, and an EEPROM; and a second IC configured to be inputted with a third voltage and a fourth voltage as outputs of the charge pump and output a fifth voltage and a sixth voltage. The second IC has a voltage regulator which regulates the third voltage and the fourth voltage or the fifth voltage and the sixth voltage and generates an eighth voltage and a ninth voltage as voltages required for programming operation or erasing operation of the EEPROM. | 08-18-2011 |
Patent application number | Description | Published |
20090004814 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved. | 01-01-2009 |
20090029522 | Method of Forming Isolation Layer of Semiconductor Device - A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material. | 01-29-2009 |
20120280397 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer. | 11-08-2012 |
Patent application number | Description | Published |
20130065457 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 03-14-2013 |
20130202948 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 08-08-2013 |
20140017554 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 01-16-2014 |
20140127545 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 05-08-2014 |
20140154550 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 06-05-2014 |
Patent application number | Description | Published |
20100237498 | PACKAGE FOR SEMICONDUCTOR DEVICE AND PACKAGING METHOD THEREOF - A semiconductor device package and a method thereof are able to reliably package a semiconductor device on a substrate without using flux. The semiconductor device package includes a semiconductor device and a substrate reciprocally disposed with respect to the semiconductor device, wherein the substrate includes a side reciprocal to the semiconductor device on which there are formed a plurality of prominences surrounding an accommodation region where the semiconductor device is to be disposed. The method of packaging a semiconductor device includes preparing the semiconductor device, preparing a substrate, forming a plurality of prominences to surround an accommodation region on the substrate where the semiconductor device is to be disposed, dropping the semiconductor device within the accommodation region, and packaging the semiconductor device on the substrate. | 09-23-2010 |
20110193231 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device. | 08-11-2011 |
20110260275 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are an electronic device package and a method of manufacturing the same. The electronic device package includes an electronic device including a polymer layer and a passivation layer configured to protect a device layer, a substrate assembly facing the electronic device, and a sealing ring formed in a closed loop between the electronic device and the substrate assembly and surrounding a sealing region. At least one side surface of the sealing ring contacts the polymer layer, and the sealing ring is disposed on the passivation layer. A polymer layer such as a microlens and a color filter is removed from a region provided with a sealing ring to form the sealing ring on a passivation layer, thereby making the sealing ring and joints the same height, thus preventing an electrical defect. | 10-27-2011 |