Patent application number | Description | Published |
20110155206 | SOLAR TILE STRUCTURE AND COMBINATION THEREOF - A solar tile structure includes a solar panel and a base. The solar panel is supported on an upper surface of the base. A protruding portion is formed on a lateral surface of a first short side of the base, a sunken portion is formed on a lateral surface of a second short side of the base, and the protruding portion of the first short side can be engaged with the sunken portion of the second short side tightly. The second short side of the base and a lateral side of the protruding portion substantially align with two lateral sides of the solar panel. | 06-30-2011 |
20110155220 | SOLAR PANEL TILE STRUCTURE AND COMBINATION THEREOF - A solar panel tile structure capable of draining water includes a solar panel and a supporting plate for supporting the solar panel. At least one draining slot is formed on the supporting plate and disposed around the solar plate for draining the water surrounding the solar panel. | 06-30-2011 |
20110168233 | SOLAR PANEL HEAT-DISSIPATING DEVICE AND RELATED SOLAR PANEL MODULE - A solar panel heat-dissipating device for adjusting temperature of a solar panel includes a base for supporting the solar panel and a cooling plate disposed between the solar panel and the base. The cooling plate includes a cooling tube contacting a side of the solar panel so as to absorb heat generated by the solar panel. In addition, conductive fluid is accommodated inside the cooling tube for dissipating the heat of the cooling tube conducted from the solar panel. | 07-14-2011 |
20130236844 | SUBSTRATE CARRIER AND SELENIZATION PROCESS SYSTEM THEREOF - A substrate carrier is used for carrying a plurality of back electrode substrates into a furnace. Each back electrode substrate has a precursor layer formed thereon. The furnace is used for providing a process gas to react with the precursor layer, so as to form a photoelectric transducing layer on each back electrode substrate. The substrate carrier includes a heat-resistant metal frame and a first protective layer. The heat-resistant metal frame has a plurality of slots for supporting the plurality of back electrode substrates. The first protective layer is formed on the heat-resistant metal frame for preventing a chemical reaction of the heat-resistant metal frame with the process gas. | 09-12-2013 |
Patent application number | Description | Published |
20090010053 | COMBO MEMORY CELL - A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors. | 01-08-2009 |
20150138869 | NON-VOLATILE MEMORY - A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. | 05-21-2015 |
Patent application number | Description | Published |
20100244066 | RED LIGHT FLUORESCENT MATERIAL AND MANUFACTURING METHOD THEREOF, AND WHITE LIGHT LUMINESCENT DEVICE - A red-light-emitting fluorescent material, suitable for being excited by a first light to emit red light, is provided. The red-light-emitting fluorescent material is characterized in the chemical formula (1): | 09-30-2010 |
20100252847 | RED LIGHT FLUORESCENT MATERIAL AND MANUFACTURING METHOD THEREOF, AND WHITE LIGHT LUMINESCENT DEVICE - A red light fluorescent material adapted for being excited by a first light to emit a red light is provided. The red light fluorescent material has the chemical formula (1) presented below, | 10-07-2010 |
20110079754 | Fabricating method of nano-powder and application thereof - A fabricating method of nano-powder is provided. First, a mixture having at least a first material and a second material is provided. Then, the mixture is sintered to obtain a single phase alloy body. After that, the single phase alloy body is pre-crumbled to obtain a powder to be ground. Then, a chemical dispersant is added into the powder to further be ground, so as to obtain the nano-powder. | 04-07-2011 |
20110084598 | Carbonitride Phosphor, Preparation Method and Light Emitting Device Thereof - A carbonitride phosphor is provided, which is represented by a general chemical formula of (M | 04-14-2011 |
20120126686 | FLOURESCENCE MATERIAL AND WHITE LIGHT ILLUMINATION ELEMENT - A fluorescence material and a white light illumination element are provided. The white light illumination element includes a light emitting diode (LED) chip, a first fluorescence material, and a second fluorescence material. The LED chip is configured on a substrate and emits an exciting light. The first fluorescence material and the second fluorescence material are configured on the LED chip. A composition of the first fluorescence material includes an aluminum nitride oxide doped with at least one of europium (Eu) and manganese (Mn). A first emitted light emitted by the first fluorescence material after the first fluorescence material absorbs the exciting light emitted from the LED chip and a second emitted light emitted by the second fluorescence material after the second fluorescence material absorbs the exciting light emitted from the LED chip are mixed to generate a white light. | 05-24-2012 |
20120168808 | PACKAGE STRUCTURE - A package structure including a first substrate, a second substrate and a light emitting diode is provided. The first substrate has at least a first annular engaged portion. The second substrate is disposed above the first substrate and has at least a second annular engaged portion. The light emitting diode is disposed on the first substrate. The second annular engaged portion is infixed to the first annular engaged portion so as to form an airtight space. The light emitting diode is located in the airtight space. | 07-05-2012 |
Patent application number | Description | Published |
20080285704 | PROGRAMMABLE INTEGER AND FRACTIONAL FREQUENCY DIVIDER - A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor. | 11-20-2008 |
20090168947 | PROGRAMMABLE INTEGER AND FRACTIONAL FREQUENCY DIVIDER - A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor. | 07-02-2009 |
20100120381 | POLAR TRANSMITTER, METHOD AND APPARATUS FOR PHASE MODULATION - A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency. | 05-13-2010 |
20100327912 | DIGITAL PHASE-LOCKED LOOP AND DIGITAL PHASE-FREQUENCY DETECTOR THEREOF - A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal. | 12-30-2010 |
20110084863 | PIPELINE TIME-TO-DIGITAL CONVERTER - A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell. | 04-14-2011 |
20120019314 | CURRENT-MODE ANALOG BASEBAND APPARATUS - A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit. | 01-26-2012 |
20120262228 | CURRENT-MODE ANALOG BASEBAND APPARATUS - A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit. | 10-18-2012 |
20130156135 | I/Q DEMODULATION APPARATUS AND METHOD WITH PHASE SCANNING - An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code. | 06-20-2013 |
Patent application number | Description | Published |
20090061143 | ORGANIC COMPOUND FOR RECORDING LAYER FOR HIGH SPEED RECORDING OF INFORMATION AND OPTICAL RECORDING MEDIUM INCLUDING THE SAME - A recording layer including a novel organic compound for a high density optical recording medium is provided. The information may be recorded on the recording layer at a 2× speed or higher speed with a relatively lower writing power so that heat distribution of the recording layer in the irradiated area is not likely to become steep both in time and space. The organic compound incorporated in the recording layer has the following general chemical structural formula (I). | 03-05-2009 |
20090087620 | ORGANIC COMPOUNDS FOR RECORDING LAYER FOR RECORDING OF INFORMATION AND OPTICAL RECORDING MEDIUM INCLUDING THE SAME - A recording layer including a novel organic compound for a high density optical recording medium is provided. The information may be recorded on the recording layer at a 2× speed or higher speed with a relatively lower writing power so that heat distribution of the recording layer in the irradiated area is not likely to become steep both in time and space. The organic compound incorporated in the recording layer has the following general chemical structural formula (I) and (II) | 04-02-2009 |
20090130593 | STABILIZER FOR ENHANCING PERFORMANCE OF OPTICAL RECORDING LAYER AND HIGH DENSITY OPTICAL RECORDING MEDIUM USING THE SAME - A recording dye layer for recording high density information and reproduction/playback of the high density information recordings is provided. The recording dye layer includes a chemical composition including a diimonium salt and or ammonium compound and a metal-azo complex for a high density optical recording medium that may effectively promote the stability and the durability of the optical recording dye layer. | 05-21-2009 |
20110157592 | SURFACE PLASMON RESONANCE UNIT AND INSPECTION SYSTEM USING THE SAME - The present invention provides a surface plasmon resonance (SPR) unit having at least one microfluidic channel with grating structures embedded in so that a grating-coupled surface plasmon resonance can be induced by an incident light while fluid in the microfluidic channel contacts or flows through the grating area. The induced variation of optical signal due to the SPR effect is analyzed for performing bio-screening and assay of bioaffinity reaction. Meanwhile, present invention further provides an SPR inspection system possessing a rotation power to the SPR unit such that the SPR unit is capable of rotating and thereby generating a centrifugal force for driving the flow inside the microfluidic channels so as to achieve the label-free and high throughput SPR inspection system with low-cost. | 06-30-2011 |
20120277123 | APPARATUS AND METHOD FOR MANUFACTURING MICROARRAY BIOCHIP - An apparatus of manufacturing a microarray biochip including a spinning platen, at least one carrier and at least one substrate is provided. The carrier is disposed on the spinning platen and includes at least one micro-channel having an input terminal and an output terminal. The substrate is attached on the output terminal of the micro-channel of the carrier. A method of manufacturing a microarray biochip with said apparatus is also provided. A sample is injected into the micro-channel through the input or the output terminal. The spinning platen is powered-on to provide a centrifugal force to the carrier, such that the sample is flowed toward the output terminal from the input terminal, and then is immobilized on the surface of the substrate. | 11-01-2012 |
20130202460 | FLUIDICS PUMPING DEVICE - A fluidics pumping device including a body and a driving assembly is provided. The body has a chamber, a channel, an inlet and an outlet. The channel goes through the chamber and connects with the inlet and the outlet. The driving assembly is disposed in the chamber, and the driving assembly has a contact surface exposed in the channel. The contact surface is suitable for moving along an extension direction of the channel, for driving a fluid in the channel. | 08-08-2013 |
Patent application number | Description | Published |
20110069420 | PROTECTION TO A POWER CONVERTER BY USING A HIGH-VOLTAGE START-UP DEVICE IN A CONTROLLER CHIP OF THE POWER CONVERTER - A controller chip provides protection to a power converter by using a high-voltage start-up device in the controller chip, without additional pins or external elements of the controller chip. A JFET is used as the high-voltage start-up device connected between a high-voltage pin and a power input pin of the controller chip, to charge a power capacitor connected to the power input pin at power on. The controller chip monitors the voltage at the power input pin and turns off the JFET once the voltage at the power input pin increases to reach a threshold. Thereafter, the source voltage of the JFET will reflect the voltage at the high-voltage pin, and a protection circuit monitors the source voltage of the JFET to trigger a protection signal. | 03-24-2011 |
20110249476 | VOLTAGE DETECTOR AND PROTECTION APPARATUS USING THE SAME - A voltage detector includes a zener diode having a cathode connected to a detect terminal of the voltage detector, a junction field effect transistor having an input terminal connected to an anode of the zener diode, and a resistor connected between an output terminal and a control terminal of the junction field effect transistor. When the voltage on the detect terminal is higher than the breakdown voltage of the zener diode, the junction field effect transistor produces a current flowing through the resistor, and thereby a detection signal can be obtained from the voltage across the resistor. | 10-13-2011 |
20130271041 | DRIVER CIRCUIT FOR IMPROVING UTILIZATION RATE OF LED DEVICE AND RELATED CONSTANT CURRENT REGULATOR - A driver circuit for driving an LED array is disclosed. The LED array includes a first, a second, a third, a fourth LED device and a diode device. The second LED device is connected to the first LED device. The fourth LED device is connected to the third LED device. The diode device is connected between the second LED device and the third LED device. The driver circuit includes a first constant current regulator for coupling between the first and the second LED device; a second constant current regulator for coupling between the second and the third LED device; a third constant current regulator for coupling between the third and the fourth LED device; a fourth constant current regulator for coupling between the fourth LED device and a fixed-voltage terminal; and a control circuit coupled with the first, the second, the third, and the fourth constant current regulators. | 10-17-2013 |
20140354163 | LED DRIVING DEVICE - An LED driving device includes: a rectifying circuit for outputting a DC voltage to a string of M LED units; (M−1) first switching circuits each coupled between a corresponding one of first to (M−1) | 12-04-2014 |
20140355320 | CONTROL CIRCUIT FOR AC-DC POWER CONVERTER - A control circuit for an AC-DC power converter includes a junction field effect transistor (JFET), a first resistor, a second resistor, and a third resistor. The JFET includes a substrate, a drain, a source, a gate, a first oxide layer, and a second oxide layer. The first oxide layer is attached to a region located between the drain and the gate of the JFET, and the second oxide layer is not attached to a region located between the drain and the gate of the JFET. The first resistor is positioned on the first oxide layer, and the second resistor and the third resistor are positioned on the second oxide layer. When the JFET and the first resistor receive an input power signal, the first, the second, and the third resistors divide the input power signal, and prevent from the breakdown of the first oxide layer and the second oxide layer. | 12-04-2014 |
Patent application number | Description | Published |
20110234188 | Buck Converter with Internal Ripple Compensation - A buck converter with internal ripple compensation includes a comparator for generating a comparison result, a constant-on-time trigger coupled to the comparator for generating a trigger control signal according to the comparison result, a pre-driver coupled to the constant-on-time trigger for controlling a high side switch and a low side switch, an output module coupled to a first node and a signal output end, and a ripple compensation circuit coupled to the high side switch, the low side switch, the first node, and the comparator for generating a compensation signal outputted to the comparator. | 09-29-2011 |
20120280671 | On-time Control Module and On-time Control Method - The present invention discloses an on-time control module for compensating a switching frequency in a switching regulator. The on-time control module includes an average voltage generating circuit, for generating an average voltage related to a duty according to an input voltage and the duty, and an on-time controller, for generating a control signal of an on-time related to the duty according to the input voltage and the duty voltage. | 11-08-2012 |
20140159680 | Bootstrap DC-DC Converter - The present invention discloses a bootstrap DC-DC converter. The bootstrap DC-DC converter includes a lower gate driver, for generating a lower gate control signal according to a control signal; a lower gate, for turning on and turning off according to a lower gate control signal; and a bootstrap voltage maintaining circuit, for generating the control signal, such that the lower gate turns on at least a minimum off time each time. | 06-12-2014 |
20150162829 | Control Module of Constant On-Time Mode and Voltage Converting Device thereof - A control module of constant on-time mode for a voltage converting device, includes a comparing unit, for generating a comparing signal according to an enhanced feedback voltage and a comparing voltage; a feedback voltage generating unit, for generating the enhanced feedback voltage according to a voltage difference between a first reference voltage and a feedback voltage corresponding to an output voltage of the voltage converting device; a comparing voltage generating unit, for generating the comparing voltage according to a second reference voltage and a control signal; and a adjusting unit, for acquiring an average voltage of the enhanced feedback voltage and adjusting the first reference voltage according to a voltage difference between the average voltage and the second reference voltage. | 06-11-2015 |
Patent application number | Description | Published |
20120257308 | Surge Protection Circuit - The present invention discloses a surge protection circuit for a line driver. The surge protection circuit includes a transistor, including a first terminal coupled to a positive output pad of the line driver and a second terminal coupled to a negative output pad of the line driver, an inverter, including an output terminal coupled to a third terminal of the transistor, and a first RC circuit, including a resistor having a terminal coupled to an input terminal of the inverter and another terminal coupled to a power supply, and a capacitor having a terminal coupled to the input terminal of the inverter and another terminal coupled to a ground. A first RC time constant of the first RC circuit is substantially equal to or greater than a period of a differential mode surge signal. | 10-11-2012 |
20140022679 | Surge Protection Circuit - A surge protection circuit for a line driver of a communication system includes a positive output pad; a negative output pad; a transistor, comprising a first terminal, a second terminal and a third terminal, the first terminal coupled to the positive output pad, the second terminal coupled to the negative output pad; and a trigger circuit. The trigger circuit includes an inverter, comprising an input terminal and an output terminal, the output terminal coupled to the third terminal of the transistor; and a first RC delay circuit. The first RC delay circuit includes a resistor having a terminal coupled to an input terminal of the inverter, and another terminal coupled to a power supply; and a capacitor having a terminal coupled to the input terminal of the inverter and another terminal coupled to a ground. The transistor is within an integrated circuit. | 01-23-2014 |
20140192908 | PARALLEL HYBRID CIRCUIT - A parallel hybrid circuit comprising a transformer, a first matching resistor, a second matching resistor and an echo cancelling circuit. The transformer comprises: a first side, comprising a transmitting coil group and a receiving coil group, wherein the transmitting coil group comprises at least one transmitting coil, wherein the receiving coil group comprises at least one receiving coil; a second side comprising at least one transceiving coil; wherein the transformer receives a transmitting signal and couples the transmitting signal from the first side to the second side via a first turn ratio, and receives a receiving signal from the transceiving line and couples the receiving signal from the second side to the first side via a second turn ratio. The first, second matching resistors are coupled with the transformer in parallel. The echo cancelling circuit is coupled between the transmitting line and the receiving line. | 07-10-2014 |
Patent application number | Description | Published |
20130303177 | INTERFERENCE MITIGATION METHOD IN CELLULAR WIRELESS NETWORK, AND APPARATUS WITH THE SAME - Interference mitigation methods in a small cell wireless network are provided. In the methods, negotiations between different stations are provided for interference mitigation. By such negotiations, UL-DL configurations are chosen in considering interference between neighboring stations and the interferences therefrom are effectively mitigated. | 11-14-2013 |
20140056383 | METHOD FOR DATA MODULATION AND TRANSMITTER USING THE SAME - A method for data transmission using spatial-domain modulation, and a transmitter using the same has been proposed. The method comprises the following steps including at least but not limited to receiving a plurality of symbols to be transmitted, mapping the symbols as L-dimensional coordinate, wherein 102-27-2014 | |
20150023260 | COMMUNICATING METHOD FOR ANTENNA ARRAY COMMUNICATION SYSTEM, USER EQUIPMENT AND BASE STATION - A communicating method for an antenna array communication system, a user equipment and a base station are provided. The communicating method includes the following steps. A plurality of beams which are formed by a plurality of antennas is transmitted by a base station, and some of the beams is selected by a user equipment. A beam set of the selected beams for the user equipment is configured by the base station. A pre-coding information is fed back to the base station according to the configured beam set by the user equipment. | 01-22-2015 |
Patent application number | Description | Published |
20100168794 | SPINAL DYNAMIC STABILIZATION DEVICE, SURGICAL METHOD UTILIZING THEREOF AND CLAMPING APPARATUS - A spinal dynamic stabilization device is provided, including at least a main portion, at least a supporting structure, and a sliding bar. The main portion includes a guiding groove. The supporting structure includes two wing portions. The wing portions pivot on the main portion. The sliding bar connects to the supporting structure and moves in the guiding groove. When the sliding bar moves in the guiding groove, the wing portions expand rotatably toward the adjacent vertebrae of the spine of the patient by the sliding bar. | 07-01-2010 |
20120004675 | DEVICE FOR FIXING SOFT TISSUE - A device for fixing soft tissue. A sleeve is detachably connected to a self-drilling tapping screw, moving and rotating the self-drilling tapping screw. A guide bar is detachably connected to the self-drilling tapping screw and fit in the sleeve. A fixing pin is fit in a washer and connected to the self-drilling tapping screw. The guide bar is detachably fit in the fixing pin. The fixing pin abuts the washer and the self-drilling tapping screw. | 01-05-2012 |
20130218209 | SPINAL DYNAMIC STABILIZATION SURGICAL METHOD - A surgical method for distracting adjacent spinal vertebrae or spinal process is disclosed. The steps of the method includes: inserting a device between the adjacent spinal vertebrae or the spinous processes, wherein the device includes at least a main portion and a stabilizing portion; and providing at least two contacts between the device and the adjacent vertebrae or the spinous processes, wherein the contacts are located on a side of vertebrae, or spinous process. | 08-22-2013 |
Patent application number | Description | Published |
20080231905 | METHOD FOR CALCULATING INK-JET PRINTING DATA - A method for calculating ink-jet printing data is disclosed. A preset pattern is first obtained. Ink-jet points required for the preset pattern are calculated to select a filtering mode. A filtering operation is implemented on the preset pattern according to the filtering mode, resulting in an applicable number of ink-jet points for the preset pattern. The preset pattern is printed on a base board based on the resulting ink-jet points. | 09-25-2008 |
20080278540 | ATMOSPHEREIC PLASMA INKJET PRINTING APPARATUSES AND METHODS FOR FABRICATING COLOR FILTER USING THE SAME - Atmospheric plasma inkjet printing apparatus and methods for fabricating color filters using the same. The atmosphere plasma inkjet printing apparatus includes a nozzle plate having a first column of nozzles and a second column of nozzles. An inkjet printhead module corresponds to the first column of nozzles. An atmospheric plasma module is corresponds to the second column of nozzles. | 11-13-2008 |
20090040591 | Electrowetting Display and Methods for Manufacturing the Same - An electrowetting display comprises a first substrate and a second substrate. A plurality of first conductive electrodes is formed over the first substrate. A second conductive layer is formed over the second substrate and spaced apart from the plurality of the first conductive electrodes. A plurality of cells is formed over the first conductive electrodes. Each cell is formed between one of the first conductive electrodes and the second conductive layer. Each two adjacent cells being separated by a partition. At least two cells include a first material and a second material over the first material. The at least two cells have two different colors. A shape of the first material is capable of being changed upon a change of an electrical field between the first conductive electrode and the second conductive layer. | 02-12-2009 |
20090185255 | ELECTRO-WETTING DISPLAY PANEL - An electro-wetting display panel including a first substrate, an insulator layer, a second substrate, partitioning structures, and electro-wetting display mediums. The first substrate has a plurality of first electrodes. The insulator layer is disposed on the first substrate to cover the first electrodes. The second substrate located above the first substrate and has a plurality of second electrodes. The partitioning structures are disposed on the insulator layer and each defines a pixel region, respectively. At least one of the partitioning structures has a flow channel surrounding the pixel regions, and the flow channel is connected to one of the pixel regions correspondingly. The electro-wetting display mediums are disposed within the pixel regions and the flow channels. When the electro-wetting display mediums are driven by the electric charge between the first electrodes and the second electrodes, the electro-wetting display mediums move between the pixel regions and the flow channels. | 07-23-2009 |
20090262165 | SUPPLY SYSTEM AND INJECTION-HEAD STRUCTURE THEREOF - A supply system capable of providing a working fluid is provided. The supply system includes an access device, a first energizer, a second energizer, a third energizer and an output device. The access device utilized to access the working fluid includes a connecting port. The first energizer provides a first energy to energize the working fluid, thereby expelling the bubbles from the working fluid. The second energizer provides a second energy to energize the working fluid received in the access device, thereby expelling the working fluid through the connecting port of the access device. The output device is connected to the access device, thereby receiving and outputting the working fluid. The third energizer provides a third energy to heat the working fluid passing through the access device and the output device. | 10-22-2009 |
20100317250 | METHOD OF FABRICATING A COLOR BACKLIGHT DEVICE - A color backlight device and fabrication method thereof is provided. A surface conduction emitter display with more than one color serves as the color backlight device. The color backlight device can be used in a liquid crystal display (LCD) to obviate the use of a color filter. The disclosure also provides a color display control method of the LCD and a pixel arrangement method of the color backlight device. | 12-16-2010 |
20120162555 | CHOLOESTERIC LIQUID CRYSTAL DISPLAY AND FABRICATION THEREOF - A cholesteric liquid crystal display is provided, including a substrate, a first electrode layer disposed on the substrate, and a liquid crystal layer disposed on the first electrode layer, wherein the liquid crystal layer comprises at least two liquid crystals having different sensitivities to driving frequencies, mixed with each other, and liquid crystals having a greater initial state-transition temperature are more sensitive to driving frequency. | 06-28-2012 |
20120206538 | SUPPLY SYSTEM AND INJECTION-HEAD STRUCTURE THEREOF - A supply system capable of providing a working fluid is provided. The supply system includes an access device, a first energizer, a second energizer, a third energizer and an output device. The access device utilized to access the working fluid includes a connecting port. The first energizer provides a first energy to energize the working fluid, thereby expelling the bubbles from the working fluid. The second energizer provides a second energy to energize the working fluid received in the access device, thereby expelling the working fluid through the connecting port of the access device. The output device is connected to the access device, thereby receiving and outputting the working fluid. The third energizer provides a third energy to heat the working fluid passing through the access device and the output device. | 08-16-2012 |
20140028963 | CHOLOESTERIC LIQUID CRYSTAL DISPLAY - A cholesteric liquid crystal display is provided, including a substrate, a first electrode layer disposed on the substrate, and a liquid crystal layer disposed on the first electrode layer, wherein the liquid crystal layer comprises at least two liquid crystals having different sensitivities to driving frequencies, mixed with each other, and the liquid crystals having a greater initial state-transition temperature are more sensitive to driving frequency. | 01-30-2014 |
Patent application number | Description | Published |
20100052808 | ACTIVE BALUN CIRCUIT - An active balun circuit is provided, which includes an input end, a first and a second output ends, a first and a second transistors, a feedback capacitor, and a current source. The input end receives an input signal. A drain of the first transistor is coupled to the second output end, and a gate of the first transistor is coupled to the input end. A gate of the second transistor is coupled to a ground end, and a drain of the second transistor is coupled to the first output end. The feedback capacitor is coupled between the second output end and the gate of the second transistor. One end of the current source is coupled to sources of the first and second transistors, and the other end of the current source is coupled to the ground end. | 03-04-2010 |
20120007673 | AMPLIFIER WITH WIDE GAIN RANGE - An amplifier with wide gain range includes a signal converting unit, a channel unit, and multiple amplifiers. The signal converting unit receives a gain modulation signal and accordingly outputs multiple modulation signals and multiple selection signals. Based on a level of the gain modulation signal, one of the selection signals is set at a first logic state and the other selection signals are at a second logic state. The channel unit has multiple channels, respectively controlled by the selection signals, so as to conduct the channel with at the first logic state. The amplifiers are connected in series. Output terminals of the amplifiers are also respectively output to the channels of the channel unit. The amplifiers are also controlled by the modulation signals of the signal converting unit. | 01-12-2012 |
20120218038 | AUTOMATIC GAIN CONTROL DEVICE HAVING FREQUENCY RESPONSE UNIT INCLUDED THEREIN AND RELATED AUTOMATIC GAIN CONTROL METHOD THEREOF - An automatic gain control device includes a variable-gain amplifier, a power detector, a gain control unit and a frequency response unit. The variable-gain amplifier is implemented for determining a gain according to a gain control signal and generating an amplified signal by amplifying a received signal according to the gain. The power detector is implemented for determining a power of a frequency response result and accordingly outputting a detection result. The gain control unit is implemented for outputting the gain control signal according to the detection result. The frequency response unit is implemented for performing a frequency response operation on the amplified signal to generate the frequency response result. | 08-30-2012 |
20130147557 | VARIABLE GAIN AMPLIFIER CIRCUIT - A variable gain amplifier circuit is disclosed. The variable gain amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first gain switching circuit, and a second gain switching circuit. The first and the second transistors are respectively coupled to the first and the second nodes for receiving a differential input signal pair. The third transistor is coupled between the first node and a third node. The fourth transistor is coupled between the second node and a fourth node. The first gain switching circuit is coupled between the first node and the third node and further cross-coupled to the fourth node. The second gain switching circuit is coupled between the second node and the fourth node and further cross-coupled to the third node. | 06-13-2013 |
20130342261 | BIAS AND LOAD CIRCUIT, FAST BIAS CIRCUIT AND METHOD - A fast bias circuit including a bias unit, a resistor, a first switch, and a detecting circuit is provided. The resistor has a first terminal coupled to the bias unit to receive a bias voltage, and a second terminal coupled to a bias terminal of a target circuit, wherein the bias terminal is coupled to an input signal. The first switch has a first terminal coupled to the first terminal of the resistor, a second terminal coupled to the second terminal of the resistor, and a control terminal coupled to the detecting circuit. During an initialisation period, the detecting circuit compares the bias voltage with a voltage at the bias terminal of the target circuit to obtain a comparison result, and controls the first switch according to the comparison result. Furthermore, a fast bias method and a bias and load circuit are also provided. | 12-26-2013 |
20150091648 | AMPLIFIER CIRCUIT AND OPERATION METHOD THEREOF - An amplifier circuit and an operation method thereof are provided. The amplifier circuit includes two stages of amplifiers. When the amplifier circuit is operated in a high gain mode, the two stages of amplifiers are operated normally to provide high gain. When the amplifier circuit is operated in a low gain mode, the second stage of amplifier is turned off, and the first stage of amplifier is coupled to output terminals of the amplifier circuit through signal isolation elements so as to form a single stage of amplifier. Therefore, the amplifier circuit can change the total gain value thereof according to a requirement of gain. | 04-02-2015 |