Patent application number | Description | Published |
20100192472 | ABRASIVE COMPOUNDS FOR SEMICONDUCTOR PLANARIZATION - A polishing slurry for semiconductor planarization containing cerium oxide particles and water, wherein the content of the cerium oxide particles having a diameter of 3 μm or more is 500 ppm or less (weight ratio) in a solid, preferably 100 ppm or less and it is more preferable that D99 (99% by volume of the whole particles in polishing slurry) of the cerium oxide particles is 1 μm or less. The polishing slurry can reduce the generation of scratches, and can polish a surface of the semiconductor substrate in the wiring formation process of semiconductor device precisely at a high speed. | 08-05-2010 |
20110006251 | CERIUM SALT, PRODUCING METHOD THEREOF, CERIUM OXIDE AND CERIUM BASED POLISHING SLURRY - A cerium salt wherein, when 20 g of the cerium salt is dissolved in a mixed liquid of 12.5 g of 6N nitric acid and 12.5 g of a 30% hydrogen peroxide aqueous solution, a concentration of an insoluble component present in the solution is 5 ppm or less by mass ratio to the cerium salt before dissolution and cerium oxide produced by processing the cerium salt at high temperatures. Scratch on a surface to be polished can be reduced when a cerium based polishing slurry containing the cerium oxide particles is used, since an amount of impurities in cerium oxide particles and cerium salt particles, raw material thereof, is reduced for high purification. | 01-13-2011 |
20110275285 | POLISHING SOLUTION FOR CMP AND POLISHING METHOD USING THE POLISHING SOLUTION - The polishing solution for CMP according to the invention comprises abrasive grains, an additive and water, and the polishing solution comprises an organic compound satisfying specified conditions as the additive. The polishing method of the invention is for polishing of a substrate having a silicon oxide film on the surface, and the polishing method comprises a step of polishing the silicon oxide film with a polishing pad while supplying the polishing solution for CMP between the silicon oxide film and the polishing pad. | 11-10-2011 |
20120315763 | POLISHING LIQUID FOR CMP AND POLISHING METHOD USING THE SAME - An object of the present invention is to provide a polishing liquid for CMP with which polishing scratches can be reduced and a sufficiently high polishing rate can be obtained in a CMP step for an ILD film, aggregation of an abrasive grain is difficult to occur, and high flatness is obtained, and provide a polishing method using the same. The polishing liquid for CMP according to the present invention is a polishing liquid for CMP containing an abrasive grain, an additive, and water, wherein the abrasive grain comprises a cerium-based particle, and the additive comprises a 4-pyrone-based compound and at least one of a nonionic surfactant or a cationic surfactant: | 12-13-2012 |
20130014446 | CERIUM SALT, PRODUCING METHOD THEREOF, SERIUM OXIDE AND CERIUM BASED POLISHING SLURRY - A cerium salt wherein, when 20 g of the cerium salt is dissolved in a mixed liquid of 12.5 g of 6N nitric acid and 12.5 g of a 30% hydrogen peroxide aqueous solution, a concentration of an insoluble component present in the solution is 5 ppm or less by mass ratio to the cerium salt before dissolution and cerium oxide produced by processing the cerium salt at high temperatures. Scratch on a surface to be polished can be reduced when a cerium based polishing slurry containing the cerium oxide particles is used, since an amount of impurities in cerium oxide particles and cerium salt particles, raw material thereof, is reduced for high purification. | 01-17-2013 |
Patent application number | Description | Published |
20090239324 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SEPARABLE SUPPORT BODY - In a method for manufacturing a semiconductor device, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer are sequentially grown on a growth substrate. Then, an electrode layer is formed on the second conductivity type semiconductor layer. Then, a support body is adhered to the electrode layer by providing at least one adhesive layer therebetween. Finally, at least a part of the growth substrate is removed. In this case, the adhesive layer is removable from the electrode layer. | 09-24-2009 |
20100148309 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device in which a selective growth mask for partially covering a growth substrate is formed on a growth substrate; a buffer layer that is thicker than the mask is formed on a non-mask part not covered by the mask on the growth substrate, and a predetermined facet is exposed on the surface of the buffer layer; a semiconductor film is laterally grown using the buffer layer as a starting point, and a lateral growth layer for covering the mask is formed while cavities are formed on the upper part of the mask; and a device function layer is epitaxially grown on the lateral growth layer. The cavity formation step includes a first step for growing a semiconductor film at a growth rate and a second step for growing another semiconductor film at another growth rate mutually different from the first growth rate, wherein the first and second steps are carried out a plurality of times in alternating fashion. | 06-17-2010 |
20100155740 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer. | 06-24-2010 |
20110175105 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF - A plurality of protrusions is formed on the C-plane substrate with a corundum structure. A base film made of a III-V compound semiconductor including Ga and N is formed on the surface of the substrate. The surface of the base film is flatter than the surface of the substrate. A light emitting structure including Ga and N is disposed on the base film. The protrusions are regularly arranged in a first direction that is tilted by less than 15 degrees with respect to the a-axis of the base film and in a second direction that is orthogonal to the first direction. Each protrusion has two first parallel sides tilted by less than 15 degrees relative to an m-axis and two second parallel sides tilted by less than 15 degrees relative to the a-axis. An interval between the two second sides is wider than an interval between the two first sides. | 07-21-2011 |
20120077298 | NITRIDE SEMICONDUCTOR CRYSTAL WITH SURFACE TEXTURE - A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range. | 03-29-2012 |
20120231608 | PRODUCTION PROCESS FOR SEMICONDUCTOR DEVICE - (a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong. | 09-13-2012 |
20130146917 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a semiconductor lamination including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer; a rhodium (Rh) layer formed on one surface of the semiconductor lamination; a light reflecting layer containing Ag, formed on the Rh layer and having an area smaller than the Rh layer; and a cap layer covering the light reflecting layer. Migration of Ag is suppressed. | 06-13-2013 |
20130153951 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a lamination of semiconductor layers including a first layer of a first conductivity type, an active layer, and a second layer of a second conductivity type; a transparent conductive film formed on a principal surface of the lamination and having an opening; a pad electrode formed on part the opening; and a wiring electrode connected with the pad electrode, formed on another part of the opening while partially overlapping the transparent conductive film; wherein contact resistance between the transparent conductive film and the lamination is larger than contact resistance between the wiring electrode and the lamination. Field concentration at the wiring electrode upon application of high voltage is mitigated by the overlapping transparent conductive film. | 06-20-2013 |
20130221384 | SEMICONDUCTOR LIGHT EMITTING ELEMENT ARRAY - A semiconductor light emitting element array contains: a support substrate; a plurality of semiconductor light emitting elements disposed on said support substrate, a pair of adjacent semiconductor light emitting elements being separated by street, each of the semiconductor light emitting elements including; a first electrode formed on the support substrate, a semiconductor lamination formed on the first electrode and including a stack of a first semiconductor layer having a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer, and having a second conductivity type different from the first conductivity type, and a second electrode selectively formed on the second semiconductor layer of the semiconductor lamination; and connection member having electrical insulating property and optically propagating property, disposed to cover at least part of the street between a pair of adjacent semiconductor laminations. | 08-29-2013 |
20130241061 | SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SAME - A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate. The method also includes forming a second bonding layer on the element structure layer to provide a second laminated body. The second bonding layer has a metal underlayer containing a metal, which forms a eutectic crystal with Au. The second bonding layer also has a surface layer that contains Au. The method also includes performing heating pressure-bonding on the first and second laminated bodies with the first and second bonding layers facing each other. The heating temperature of the second substrate in the heating pressure-bonding is higher than the heating temperature of the first substrate. | 09-19-2013 |
20130244361 | METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A method of manufacturing a semiconductor element includes forming an element structure layer having a semiconductor layer, on a first substrate. The method also includes forming a first bonding layer on the element structure layer. The method also includes forming a second bonding layer on a second substrate. The method also includes performing heating pressure-bonding on the first and second bonding layers, with the first and second bonding layers facing each other. One of the first bonding layer and the second bonding layer is an AU layer, and the other is an AuSn layer. The AuSn layer has a surface layer having an Sn content of between 85 wt % (inclusive) and 95 wt % (inclusive). | 09-19-2013 |
20130248918 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions. | 09-26-2013 |