Patent application number | Description | Published |
20080314633 | Printed circuit board - A printed circuit board, which increases the contact area between an IC and a printed circuit board, thus increasing the degree of adhesion, is disclosed. The printed circuit board includes: an insulation layer which includes a first circuit pattern, including at least one via land, embedded in the upper surface of the insulation layer to be flush with the upper surface, and a second circuit pattern formed in the lower surface of the insulation layer to be flush with the lower surface; a solder resist layer formed on the insulation layer; a via hole and a bump integrally formed on the second circuit pattern through the via hole and the via land such that it protrudes from the insulation layer to be higher than the solder resist layer. | 12-25-2008 |
20090027864 | Printed circuit board and manufacturing method thereof - A printed circuit board and a method of manufacturing the printed circuit board are disclosed. A printed circuit board, which includes an insulation layer, a circuit pattern formed on a surface of the insulation layer that includes at least one pad, and a solder resist which covers the circuit pattern, and in which an opening is formed that exposes a portion of a side and a surface of the pad, can ensure a sufficient amount of attachment area for the pads and the solder resist, to strengthen the adhesion of the pads. Also, the adhesion can be increased between the electronic components and the printed circuit board, and heat release characteristics can be improved. | 01-29-2009 |
20090097220 | Printed circuit board - A printed circuit board is disclosed. The printed circuit board, which has at least one pad on which a solder ball is to be placed, includes a solder resist that covers a surface of the printed circuit board, an opening part that exposes the pad and supports the solder ball, and an extended portion formed in a perimeter of the opening part that allows an underfill to flow in between the printed circuit board and the solder ball. With this printed circuit board, the underfill can be filled in more readily between the printed circuit board and the solder balls, when mounting a component on the printed circuit board. | 04-16-2009 |
20110286191 | Printed circuit board and semiconductor package with the same - Disclosed herein is a printed circuit board. The printed circuit board includes a base substrate including a first region on which a semiconductor chip is mounted and a second region positioned outside the first region, first insulating patterns covering the base substrate and including trenches formed on the second region, and second insulating patterns protruding from the first insulating patterns on the second region. The trench and the second insulating pattern may be used as a structure defining an underfill forming material in a preset shape during the process of forming an underfill. | 11-24-2011 |
20110297423 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base substrate, a first bump including a first metal layer formed on the base substrate and a second metal layer formed on the first metal layer, and a second bump including a third metal layer formed on the base substrate, in which the first bump has a height greater than that of the second bump. Because the heights of the first bump and the second bump are different, even when the printed circuit board warps, an electrical connection between the printed circuit board and an external substrate does not become broken. A method of manufacturing the printed circuit board is also provided. | 12-08-2011 |
Patent application number | Description | Published |
20140131857 | BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE - Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized. | 05-15-2014 |
20140138831 | SURFACE FINISH ON TRACE FOR A THERMAL COMPRESSION FLIP CHIP (TCFC) - Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is | 05-22-2014 |
20140159238 | PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD - Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate. | 06-12-2014 |
20140175658 | ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE - Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer. | 06-26-2014 |
20140247573 | PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES - Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (nm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball. | 09-04-2014 |
20140264946 | PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT - To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window. | 09-18-2014 |
20140322868 | BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE - Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized. | 10-30-2014 |
20140356635 | SUBSTRATE COMPRISING INORGANIC MATERIAL THAT LOWERS THE COEFFICIENT OF THERMAL EXPANSION (CTE) AND REDUCES WARPAGE - Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage. | 12-04-2014 |
20150061143 | ULTRA FINE PITCH AND SPACING INTERCONNECTS FOR SUBSTRATE - Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer. | 03-05-2015 |