Patent application number | Description | Published |
20080242043 | METHOD FOR CHECKING ALIGNMENT ACCURACY USING OVERLAY MARK - A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation. | 10-02-2008 |
20080268350 | SEMICONDUCTOR STRUCTURE - A photomask is provided. The photomask includes a device pattern region, a die sealing pattern region and at least two alignment mark patterns. The device pattern region has a first side and a second side and the first side is opposite to the second side. The die sealing pattern region surrounds the device pattern region. The alignment mark patterns includes a first overlay mark pattern and a second overlay mark pattern and the first overlay mark pattern and the second overlay mark pattern are located outside the device pattern region and at the first side and second side respectively. An arrangement relationship between the first overlay mark pattern and the first side is a mirror of an arrangement relationship between the second overlay mark pattern and the second side. | 10-30-2008 |
20080292974 | EXPOSURE PROCESS AND PHOTOMASK SET USED THEREIN - An exposure process is described, for defining in a photoresist layer a plurality of first patterns having a first pitch and a second pattern between them that is wider than one first pattern. A first exposure step is conducted to the photoresist layer with a first photomask that has a plurality of the first patterns without a second pattern between them, wherein the first patterns on the first photomask have the first pitch only. A second exposure step is conducted to the photoresist layer with a second photomask that has a third pattern narrower than the second pattern at a position corresponding to the second pattern. The exposure dose of the first or second exposure step alone is not sufficient to define any pattern in the photoresist layer. | 11-27-2008 |
20080304063 | OVERLAY MARK AND APPLICATION THEREOF - An overlay mark is described, wherein the overlay mark is used for checking the alignment accuracy between a lower layer defined by two exposure steps and a lithography process for defining an upper layer, including a part of the lower layer and a photoresist patter. The part of the lower layer includes two first x-directional, two first y-directional bar-like patterns. The first x-directional and first y-directional bar-like patterns are defined by one exposure step to define a first rectangle. The second x-directional and second y-directional bar-like patterns are defined by another exposure to define a second rectangle, wherein the second rectangle is wider than the first rectangle. The photoresist pattern, which is formed by the lithograph process, is disposed over the part of the lower layer and is surrounded by the bar-like patterns. | 12-11-2008 |
20080315373 | METHOD OF ENABLING ALIGNMENT OF WAFER IN EXPOSURE STEP OF IC PROCESS AFTER UV-BLOCKING METAL LAYER IS FORMED OVER THE WHOLE WAFER - A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed. | 12-25-2008 |
20090068843 | METHOD OF FORMING MARK IN IC-FABRICATING PROCESS - A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps. | 03-12-2009 |
20090096116 | ALIGNMENT MARK AND MEHTOD FOR FORMING THE SAME - The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements. | 04-16-2009 |
20090104564 | PATTERNING PROCESS - The invention is directed to a method for patterning a material layer. The method comprises steps of forming a mask layer on the material layer. A multiple patterning process is performed on the mask layer for transferring at least a first pattern from a first photomask through a first photoresist and a second pattern from a second photomask from a second photoresist layer into the mask layer without performing any etching process. The mask layer exposes a portion of the material layer and the mask layer is patterned at the time that the first photoresist layer and the second photoresist layer are developed respectively. An etching process is performed to pattern the material layer by using the mask layer as an etching mask. | 04-23-2009 |
20090130612 | PATTERNING PROCESS - The invention is directed to a method for patterning a material layer. The method comprises steps of forming a first mask layer on the material layer and then patterning the first mask layer. The patterned first mask layer has a pattern therein and a plurality of gaps within the patterns and the gaps expose a portion of the material layer. Further, a second mask layer is formed over the material layer and the second mask layer fills the gaps. An interface layer is formed between the patterned first mask layer and the second mask layer. A portion of the second material layer is removed until the top surface of the interface layer is exposed. The interface layer is removed to expose a portion of the material layer and the material layer is patterned by using the patterned first mask layer and the second mask layer as a mask. | 05-21-2009 |
20090134531 | OVERLAY MARK AND METHOD FOR FORMING THE SAME - The invention is directed to an overlay mark in a first material layer in an overlay alignment region of a wafer and the first material layer is made from a first material. The overlay mark includes a plurality of mark regions and each of the mark regions comprises a plurality mark elements embedded in the first material layer. Each of the mark elements is made of a second material different from the first material of the first material layer and the mark elements evenly distribute in the mark region. | 05-28-2009 |
20090286407 | BAKING APPARATUS, BAKING MEHOD AND METHOD OF REDUCING GAP WIDTH - A baking apparatus including a hot plate and a substrate rotation member is provided. The hot plate has a heating surface. The substrate rotation member includes a rotation ring and a plurality of support arms. The rotation ring is configured to surround the hot plate. The support arms are disposed over the heating surface of the hot plate. Each of the support arms includes a connection part and a support part, wherein the connection part is configured to connect the rotation ring and the support part, and a supporting surface of the support part for supporting the substrate is higher than the heating surface of the hot plate. | 11-19-2009 |
20100002933 | OVERLAY MARK, METHOD OF CHECKING LOCAL ALIGMNENT USING THE SAME AND METHOD OF CONTROLLING OVERLAY BASED ON THE SAME - An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (≧2) exposure steps and N sets of parallel y-directional linear patterns respectively defined by the N exposure steps, and a set of parallel x-directional photoresist bars and a set of parallel y-directional photoresist bars both formed in a lithography process. The N sets of x-directional linear patterns and the set of x-directional photoresist bars are arranged in parallel. The N sets of y-directional linear patterns and the set of y-directional photoresist bars are arranged in parallel. | 01-07-2010 |
20100035191 | METHOD FOR PATTERNING MATERIAL LAYER - The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask. | 02-11-2010 |
20100068657 | METHOD OF PATTERNING TARGET LAYER ON SUBSTRATE - A method of patterning a target layer on a substrate is described. A patterned photoresist layer is formed over the target layer, wherein the patterned photoresist layer has unexposed parts as separate islands and each unexposed part has a low proton concentration at least in its sidewalls. Acid-crosslinked polymer layers are formed only on the sidewalls of each unexposed part. A flood exposure step is performed to the substrate. A baking step is performed to the patterned photoresist layer. A development step is performed to remove the previously unexposed parts. The target layer is etched with the acid-crosslinked polymer layers as a mask. | 03-18-2010 |
20100310342 | METHOD AND APPARATUS FOR TRANSFERRING SUBSTRATE - A method and an apparatus for transferring a substrate are described. In the method, a substrate is provided on the surface of a first plate at a first position, the first plate is moved from the first position to a second position in an upper space of a second plate, the substrate is lifted away from the surface of the first plate, the first plate is moved away from the second position, and the substrate is put on the surface of the second plate from the upper space. The apparatus includes a first plate and a second plate each having a surface for carrying the substrate, wherein the first plate can be moved between the first position and the second position. | 12-09-2010 |
20110089578 | WAFER STRUCTURE - A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark. | 04-21-2011 |
20110169175 | OVERLAY MARK - An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape. | 07-14-2011 |
20110191728 | INTEGRATED CIRCUIT HAVING LINE END CREATED THROUGH USE OF MASK THAT CONTROLS LINE END SHORTENING AND CORNER ROUNDING ARISING FROM PROXIMITY EFFECTS - An integrated circuit that includes a line end created through use of a mask that controls line end shortening and corner rounding arising from proximity effects is provided. The mask includes a main feature having opaque and transmissive areas arranged to reflect a patterned feature of the line end, at least one of an opaque edge or a transmissive edge located at each end of the main feature, wherein the opaque edge has a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge has a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature. | 08-04-2011 |
20110263125 | METHOD OF FORMING MARK IN IC-FABRICATING PROCESS - A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps. | 10-27-2011 |