Chih-Nan
Chih-Nan Chen, Taoyuan County TW
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20130008288 | METHOD FOR CONTROLLING BETA-TIN ORIENTATION IN SOLDER JOINTS - A method for controlling the beta-tin crystal orientation in solder joints is provided. The method is suitable for joining metallization pads using a solder containing tin and silver. By adjusting the silver content in the solder within a specific range of equal to or more than 2.5 wt. % and less than 3.2 wt. %, the [001] axes of beta-tin crystals in the solder is aligned to be in the direction parallel with a solder/metallization pad interface substantially. Electromigration-induced solder deformations and metallization pad consumption can be significantly reduced when solder joints have such a microstructure. Additionally, the undesired Ag | 01-10-2013 |
Chih-Nan Cheng, Hsinchu TW
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20150041920 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND MANUFACTURING METHOD THEREOF - An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are arranged on a P-substrate, and each NMOS element includes a gate, a source, and a drain. The source and the drain are arranged on two opposite sides of the gate. The doped region is implanted into an outer space of the two NMOS surrounding the two NMOS, and a PN junction is formed by the doped region and the P-substrate. | 02-12-2015 |
20150049404 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND INTEGRATED CIRCUIT USING SAME - An electrostatic discharge (ESD) protection device is formed in an integrated circuit (IC) with a DC-DC converter. The DC-DC converter includes a high-side switch and a low-side switch in series. The ESD protection device includes a first ESD protection component coupled to the high-side switch in parallel and a second ESD protection component coupled to the low-side switch in parallel. When an ESD occurs, the first ESD protection component is turned on before the high-side switch functions and the second ESD protection component is turned on before the low-side switch functions. | 02-19-2015 |
20150061616 | SWITCHING POWER VOLTAGE REGULATOR - A switching power voltage regulator includes a pulse width modulation (PWM) signal generator, an output circuit and a feedback circuit. The PWM signal generator is configured to generate a PWM signal. The feedback circuit is configured to provide a feedback signal to the output circuit according to an output voltage of the output circuit. The output circuit includes an inductor, a plurality of inverters, and a driver. Each of the inverters includes a first transistor and a second transistor. When the inductor needs to be charged, the driver selectively switches one or more corresponding first transistors on according to the feedback signal. | 03-05-2015 |
20150091049 | TRIODE - A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region. | 04-02-2015 |
20150091050 | TRIODE - A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel. | 04-02-2015 |
Chih-Nan Cheng, I-Lan Hsien TW
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20090020812 | METAL-OXIDE-SEMICONDUCTOR DEVICE - A MOS device includes a semiconductor substrate having a first conductive type, a source region, a gate structure, and a drain region having a second conductive type. The gate structure is formed on the semiconductor substrate and substantially parallel to a first direction. The source region and the drain region are both disposed in the semiconductor substrate, and on two opposite sides of the gate structure. The source region includes at least a source doped region having the second conductive type, and at least a source contact region having the first conductive type, and the source doped region and the source contact region are alternately arranged along the first direction. | 01-22-2009 |
Chih-Nan Liang, Changhua County TW
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20080203057 | WET CLEANING PROCESS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A wet cleaning process is provided. The wet cleaning process includes at least one first rinse process and a second rinse step. The first rinse step includes rinsing a substrate using deionized water containing CO | 08-28-2008 |
Chih-Nan Wei, Kaohsiung TW
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20110080534 | LIGHT COMPENSATION SCHEME, OPTICAL MACHINE DEVICE, DISPLAY SYSTEM AND METHOD FOR LIGHT COMPENSATION - A light compensation scheme, an optical machine device, a display system and a method for light compensation are disclosed herein. The light compensation scheme includes a detector for inspecting a data related to a luminous flux of each of different color beams, and a controller for selectively adjusting anytime a luminosity of at least one of a plurality of pointolites and/or the transmittances of at least one part of liquid crystals disposed within a liquid crystal display panel, based on the inspected data. | 04-07-2011 |
Chih-Nan Wu, Hsin-Chu TW
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20160141179 | Selective Growth for High-Aspect Ration Metal Fill - An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition. | 05-19-2016 |
Chih-Nan Wu, Tainan City TW
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20140263956 | High-K Dielectric Grid Structure for Semiconductor Device - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface, a plurality of sensor elements disposed at the front surface of the substrate. Each of the plurality of sensor elements is operable to sense radiation projected towards the back surface of the substrate. The image sensor also includes a high-k dielectric grid disposed over the back surface of the substrate. The high-k dielectric grid has a high-k dielectric trench and sidewalls. The image sensor also includes a color filter and a microlens disposed over the high-k dielectric grid. | 09-18-2014 |
20160111325 | ETCH STOP LAYER IN INTEGRATED CIRCUITS - An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer. | 04-21-2016 |
Chih-Nan Yen, Hsichu TW
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20150012801 | METHOD OF DETECTING AND CORRECTING ERRORS WITH BCH AND LDPC ENGINES FOR FLASH STORAGE SYSTEMS - A method of detecting and correcting errors with BCH and LDPC engines for flash storage systems is provided and the steps of the method comprise: deciding the number i of sub-channels CH1˜CHi divided from the data channel depending on requirement; deriving the width selection of each sub-channel CHi; checking if the sum of width of each sub-channel CHi is equal to the length of the original channel | 01-08-2015 |