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| 20140014839 | SENSOR DESIGN BASED ON LIGHT SENSING - A sensor based on light sensing is provided, including a visible light sensor, an IR sensor, an amplifier connected to visible light sensor and IR sensor, an auto-gain control (AGC) connected to amplifier, an A/D converter (ADC) connected to AGC, a digital filter connected to ADC, a multiplexer connected to both digital filter and ADC, a timing controller connected to amplifier, AGC, DC, and digital filter, a temperature sensor, a voltage reference connected to amplifier, an oscillator connected to ADC, an IR_LED driver for driving IR LEDs, a control register connected to timing controller, a data register connected to multiplexer, an I2C interface connected to external serial clock line (SCL) and serial data lines (SDA), and an interrupt interface connected to external interrupt bus (INTB). SCL, SDA and INTB are connected externally to a host able to read and display the result data from the sensor. | 01-16-2014 |
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| 20150075515 | BARBECUE GRILL WITH MULTIFUNCTION - A barbecue grill includes a body, a support and a platform frame. The body is mounted in the support, and the support is erected on the platform frame. The body defines an oven chamber. An oil discharge port is arranged at a bottom of the oven chamber. A plurality of keys are arranged near an opening on the inner sidewall of the oven chamber. A barbecue plate is arranged in the body, and the edge of the barbecue plate rests on the plurality of keys. A burner is arranged in the body, and is located below the barbecue plate. The platform frame includes an oven platform and a stand mounted at the bottom of the oven platform. The support is erected on the oven platform. The oven platform defines a groove for placement of the barbecue plate. A slot is defined on the oven platform to support legs. | 03-19-2015 |
| 20150114383 | Portable Barbecue Grill - A barbecue grill includes an oven, a supporting member, and a pair of holders. The supporting member includes a panel, a first stand, and a second stand in cross connection with the first stand and pivoting on the first stand. One end of the first stand pivots on a bottom of the panel, and one end of the second stand is fixed with the bottom of the panel. The pair of holders support the oven, one end of each of the pair of holders pivots on a bottom of the oven, and another end of each of the pair of holders is fixed on the supporting member. When the pair of holders are detached from the panel, the pair of holders stack on the bottom of the oven, and when the second stand is detached from the panel, the second stand and the panel stack on the first stand. | 04-30-2015 |
| 20150238048 | BARBECUE GRILL - The present invention relates to the technical field of a barbecue utensil and discloses a barbecue grill including a barbecue grill body having a cavity with an opening in an upper end, a heating furnace head and a hot plate are disposed in the cavity, and a barbecue wire mesh is disposed on the opening of the cavity, the hot plate covers the whole top of the heating furnace head and is provided with a plurality of ventilation holes, and an upper surface of the hot plate is inclined and is provided with a plurality of covering plates on the positions corresponding to the ventilation holes, each covering plate covers the whole top of the ventilation hole, one end of the covering plate is connected to an upper surface of the hot plate and the other end extends slantwise downwards and a gap is disposed between the upper surface of the hot plate and the other end of the covering plate. | 08-27-2015 |
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| 20150044008 | Robot Blade Design - The present disclosure relates to a wafer transfer robot having a robot blade that can be used to handle substrates that are patterned on both sides without causing warpage of the substrates. In some embodiments, the wafer transfer robot has a robot blade coupled to a transfer arm that varies a position of the robot blade. The robot blade has a wafer reception area that receives a substrate. Two or more spatially distinct contact points are located at positions along a perimeter of the wafer reception area that provide support to opposing edges of the substrate. The two or more contact points are separated by a cavity in the robot blade. The cavity mitigates contact between a backside of the substrate and the robot blade, while providing support to opposing sides of the substrate to prevent warpage of the substrate. | 02-12-2015 |
| 20150069539 | Cup-Like Getter Scheme - The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased. | 03-12-2015 |
| 20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 03-12-2015 |
| 20150102432 | Method of Improving Getter Efficiency by Increasing Superficial Area - The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process. | 04-16-2015 |
| 20160101976 | METHOD OF IMPROVING GETTER EFFICIENCY BY INCREASING SUPERFICIAL AREA - In some embodiments, the present disclosure relates to a MEMs (micro-electromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process. | 04-14-2016 |
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| 20100060526 | OMNIDIRECTIONAL ANTENNA - An omnidirectional antenna includes a substrate, a signal feed-in portion, a first radiation unit, and a second radiation unit. The first radiation unit is located on a first surface of the substrate, and electrically connected to a first circuit of the first surface. The first radiation unit has a first extension end and a second extension end. The second radiation unit is located on a second surface of the substrate, and electrically connected to a second circuit of the second surface. The second radiation unit has a third extension end and a fourth extension end. The first extension end is disposed corresponding to the third extension end, and the second extension end is disposed corresponding to the fourth extension end. The signal feed-in portion is located on the first circuit and the second circuit. Thus, the impedance is improved, a wider bandwidth is achieved, and the process is simplified. | 03-11-2010 |
| 20100123637 | ANTENNA - An antenna includes a substrate, a signal feed portion, and a plurality of radiation units. The substrate has a first surface and a second surface. The signal feed portion is located on the substrate. The plurality of radiation units is located on the substrate, connected to the signal feed portion, and arranged in a radial shape. Each of the radiation units includes a radiation portion and a ground portion. The radiation portion is located on the first surface with one end connected to the signal feed portion. The ground portion is located on the second surface in symmetry with the radiation portion, with one end connected to the signal feed portion. A plurality of dipole antennas connected in parallel to the signal feed portion, so as to avoid a zero point generated on the single dipole antenna, such that a wave width of the antenna radiation has a large angle. | 05-20-2010 |
| 20100149063 | DUAL-FREQUENCY ANTENNA - A dual-frequency antenna includes a substrate, a ground layer, a plurality of signal feed portions, at least one first radiation portion, a plurality of second radiation portions, a plurality of first signal transmission lines, a plurality of second signal transmission lines, a plurality of first filters, and a plurality of second filters. The signal feed portions are disposed between the first radiation portions and the second radiation portions that are disposed on the first surface of the substrate in a staggered manner. The first signal transmission lines and the second signal transmission lines are respectively used to connect the signal feed portions with the first radiation portions and the second radiation portions. The first filters and the second filters are respectively disposed on the first signal transmission lines and the second signal transmission lines. The dual-frequency antenna is applicable for providing broadband and high gain features. | 06-17-2010 |
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| 20140320172 | CURRENT-TO-VOLTAGE CONVERTER AND ELECTRONIC APPARATUS THEREOF - A current-to-voltage converter comprises a gain circuit, a flip circuit, and a chopper circuit. The gain circuit receives an input current, and amplifies the input current to generate an amplified current. The flip circuit receives the amplified current, and uses the amplified current to charge or discharge a capacitor thereof according to a charge signal and a discharge signal, so as to generate an output voltage, wherein before using the amplified current to charge or discharge the capacitor, the flip circuit resets the output voltage respectively to a charge reset voltage and a discharge reset voltage according to a charge reset signal and a discharge reset signal. When the capacitor is charged, the chopper circuit samples and holds the output voltage to generate a recovered voltage. When the capacitor is discharged, the chopper circuit samples, holds, and flips the output voltage to generate the recovered voltage. | 10-30-2014 |
| 20140333348 | CURRENT-TO-VOLTAGE CONVERTER AND ELECTRONIC APPARATUS THEREOF - A current-to-voltage converter which is used to receive an input current and to generate an output voltage accordingly comprises a current tracking bias circuit, a current-to-voltage unit, and a voltage clamp bias circuit. The current tracking bias circuit generates a first bias according to the input current. The current-to-voltage unit receives the first bias and the input current, and generates the output voltage according to the input current, wherein the first bias determines a range of the input current, the current-to-voltage unit has a first current control device, and the first current control device changes a current conduction level thereof in response to the first bias, such that a rising or falling speed of the output voltage is enhanced. The voltage clamp bias circuit clamps voltage levels of two ends where the voltage clamp bias circuit is connected to the current-to-voltage unit. | 11-13-2014 |
| 20150029137 | NOISE COMPENSATING TOUCH PANEL AND TOUCH DEVICE THEREOF - A noise compensating touch panel includes a touch module and a signal compensating module. The touch module includes transmission electrodes and sensing electrodes. The signal compensating module has a first input, a second input and an output. The signal compensating module couples to the touch module. The transmission electrodes receive scanning voltage signals sequentially. When the scanning voltage signals sense the touching by object at crossover points of a first transmission electrode and the sensing electrodes, the sensing electrodes provide sensing signals. The sensing signals include the value of a first parasitical capacitor. The second transmission electrode senses the value of a second parasitical capacitor which the second transmission electrode isn't touched by object when the second transmission electrode receives the scanning voltage signals. Then the second transmission electrode provides compensating signals. Signal compensating module receives the sensing signals and the compensating signals separately. | 01-29-2015 |
| 20150062092 | BASELINE CALIBRATION METHOD AND SYSTEM THEREOF FOR TOUCH PANEL - An exemplary embodiment of the present disclosure illustrates a baseline calibration method for touch panel. Firstly, the baseline calibration method calculates each first differential value associated with each respective transmission electrode through a first-axis calculation procedure. Next, the baseline calibration method calculates each second differential value associated with each respective sensing electrode through a second-axis calculation procedure. Finally, the baseline calibration method calculates a baseline calibration value based on each of the first differential values and each of the respective second differential values calculated. | 03-05-2015 |
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| 20090039424 | HIGH-VOLTAGE MOS TRANSISTOR DEVICE - A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings. | 02-12-2009 |
| 20090039425 | HIGH-VOLTAGE MOS TRANSISTOR DEVICE - A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device. | 02-12-2009 |
| 20090159966 | High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate - A high voltage semiconductor device comprises a substrate, a well, a gate structure, and a source/drain structure in a grade region in a well in the substrate. The gate structure is disposed on the substrate with a portion vertically down into a trench in the well in the substrate and has a relatively small size. The method of fabricating the high voltage semiconductor device comprises forming a first trench for an STI structure and a second trench for a gate structure, depositing an oxide layer on the substrate to fill the first and the second trenches, wherein a void is formed in the second trench, performing a photolithography and etching process to remove a portion of the oxide layer in the second trench, and forming a gate on the gate dielectric layer in the second trench. | 06-25-2009 |
| 20110250727 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing flash memory device is provided and includes the following steps. First, a substrate is provided. Then, a stacked gate structure is formed on the substrate. Subsequently, a first oxide layer is formed on the stacked gate structure. Following that, a nitride spacer is formed on the first oxide layer, wherein a nitrogen atom-introducing treatment is performed after the forming of the first oxide layer and before the forming of the nitride spacer. Accordingly, the nitrogen atom-introducing treatment of the presentation invention can improve the data retention reliability of the flash memory device. | 10-13-2011 |
| 20110309434 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate. | 12-22-2011 |
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| 20150048448 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. | 02-19-2015 |
| 20150123199 | LATERAL DIFFUSED SEMICONDUCTOR DEVICE - A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region. | 05-07-2015 |
| 20150200261 | SEMICONDUCTOR DEVICE WITH A STEP GATE DIELECTRIC STRUCTURE - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. A method for forming a semiconductor device is also disclosed. | 07-16-2015 |
| 20150279986 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device. | 10-01-2015 |
| 20150295018 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed. | 10-15-2015 |
| 20150295026 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a portion of the semiconductor layers along a first direction; a gate structure disposed over a portion of the semiconductor layers along a second direction, wherein the gate structure covers a portion of the composite doped regions; a first doped region formed in the most top semiconductor layer along the second direction and being adjacent to a first side of the gate structure; and a second doped region formed in the most top semiconductor layer along the second direction and being adjacent to a second side of the gate structure opposite to the first side thereof. | 10-15-2015 |
| 20150295032 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device. | 10-15-2015 |
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| 20130234229 | SINGLE POLY ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (SINGLE POLY EEPROM) DEVICE - A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation. | 09-12-2013 |
| 20140319622 | SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME - A semiconductor device is disclosed. An isolation structure is formed in a substrate to define an active region of the substrate, wherein the active region has a field plate region. A gate dielectric layer is formed on the substrate outside of the field plate region. A step gate dielectric structure is formed on the substrate corresponding to the field plate region, wherein the step gate dielectric structure has a thickness greater than that of the gate dielectric layer and less than that of the isolation structure. A method for forming a semiconductor device is also disclosed. | 10-30-2014 |
| 20150243766 | METHOD AND APPARATUS FOR POWER DEVICE WITH MULTIPLE DOPED REGIONS - A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type. | 08-27-2015 |
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| 20090096039 | HIGH-VOLTAGE DEVICE AND MANUFACTURING METHOD OF TOP LAYER IN HIGH-VOLTAGE DEVICE - A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the substrate, and the well is disposed in the substrate at one side of the gate. The source region is disposed in the substrate at the other side of the gate. The drain region is disposed in the well of the substrate. The conductive layers are disposed on the substrate between the gate and the drain region. The top layer is disposed in the well of the substrate, and the well is below the conductive layers. One portion of the top layer near the gate has a thickness greater than that of the other portion of the top layer away from the gate. | 04-16-2009 |
| 20090111252 | METHOD FOR FORMING DEEP WELL REGION OF HIGH VOLTAGE DEVICE - A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions. | 04-30-2009 |
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| 20120266609 | CAN HEATING AND COOLING DEVICE - An exemplary can heating and cooling device includes a container made of thermally conductive material, a heat spreader with a heat spreading portion and a heat exchanging portion, and a heat exchanger with a thermoelectric cooling chip and a heat sink. The container includes an outer side wall with a planar thermal contacting section of the container. The heat spreading portion of the heat spreader contacts the outer side wall of the container. The heat exchanging portion of the heat spreader contacts the planar thermal contacting section of the container. The thermoelectric cooling chip includes a first surface thermally connected with the heat exchanging portion of the heat spreader, and a second surface thermally connected with the heat sink. | 10-25-2012 |
| 20130105124 | HEAT DISSIPATION FAN | 05-02-2013 |
| 20130170968 | HEAT DISSIPATING FAN WITH LATERAL AIR INLET AND OUTLET - An exemplary heat dissipating fan includes a frame and an impeller rotatablely received in the frame. The frame includes a base and a top cover disposed on the base, the base includes a bottom plate a peripheral sidewall. The sidewall extends between the bottom plate and the top cover, and the base and the top cover cooperatively defines a receiving space. The impeller is rotatably received in the receiving space. The top cover, the bottom cover and the sidewall cooperatively defines an air inlet therebetween. The top cover, the bottom plate and the sidewall cooperatively defines an outlet therebetween. The air outlet is generally adjacent to and substantially perpendicular to the air inlet. | 07-04-2013 |
| 20130213615 | HEAT DISSIPATION DEVICE WITH CONVECTION DRIVEN IMPELLER - An exemplary heat dissipation device includes a base, spaced fins, a bracket, a shaft and a first impeller. The base directly contacts a heat-generating source. The fins are mounted on the base to dissipate heat transferred from the base by nature convection and thermal radiation. The bracket is mounted on the fins and includes a rotor. The shaft is engaged with the rotor and is located above of the fins. The first impeller is located at above of the bracket and engaged with a top end of the shaft. Heat generated by the heat-generating source is absorbed by the base and then is transferred to the fins for dissipation. Air around the fins and the base is heated and moves upwards to drive the first impeller to rotate. | 08-22-2013 |
| 20140099197 | CENTRIFUGAL FAN WITH ANCILLARY AIRFLOW OPENING - An exemplary centrifugal fan includes a housing and an impeller received in the housing. The housing defines an air inlet and an air outlet thereof. Airflow driven by the impeller flows out of the housing via the air outlet. The housing further defines an opening adjacent to one end of the air outlet. The ambient air out of the centrifugal fan enters the housing via the opening, and flows out of the housing via the air outlet. | 04-10-2014 |
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| 20130076385 | Semiconductor Test Structures - A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension. | 03-28-2013 |
| 20130107248 | ENHANCED DEFECT SCANNING | 05-02-2013 |
| 20140162534 | POLISHING SYSTEM AND POLISHING METHOD - A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. | 06-12-2014 |
| 20140203282 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 07-24-2014 |
| 20140206113 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 07-24-2014 |
| 20140246758 | NITROGEN-CONTAINING OXIDE FILM AND METHOD OF FORMING THE SAME - A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %). | 09-04-2014 |
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| 20100270636 | ISOLATION STRUCTURE FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated image sensor includes an isolation structure passing through a substrate, a sensor element formed overlying the front surface of the substrate, and a color filter formed overlying the back surface of the substrate. | 10-28-2010 |
| 20100279459 | METHOD FOR REDUCING CONTACT RESISTANCE OF CMOS IMAGE SENSOR - A method for performing a CMOS Image Sensor (CIS) silicide process is provided to reduce pixel contact resistance. In one embodiment, the method comprises forming a Resist Protect Oxide (RPO) layer on the CIS, forming a Contact Etch Stop Layer (CESL), forming an Inter-Layer Dielectric (ILD) layer, performing contact lithography/etching, performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at pixel contact hole area, performing contact filling, and defining the first metal layer. The Resist Protect Oxide (RPO) layer can be formed without using a photo mask of Cell Resist Protect Oxide (CIRPO) photolithography for pixel array and/or without silicide process at pixel array. The method can include implanting N+ or P+ for pixel contact plugs at the pixel contact hole area. The contact filling can comprise depositing contact glue plugs and performing Chemical Mechanical Polishing (CMP). | 11-04-2010 |
| 20120288982 | METHOD FOR REDUCING CONTACT RESISTANCE OF CMOS IMAGE SENSOR - This description relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at the pixel contact hole area and performing contact filling. This description also relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes implanting N+ or P+ for pixel contact plugs at a pixel contact hole area, performing Physical Vapor Deposition (PVD) at pixel contact hole area, annealing for silicide formation at the pixel contact hole area, performing contact filling and depositing a first metal film layer, wherein the first metal film layer links contact holes for a source, a drain, or a poly gate of a CMOS device. | 11-15-2012 |
| 20140030866 | METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER - A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided. | 01-30-2014 |
| 20140151835 | BACKSIDE ILLUMINATED IMAGE SENSORS AND METHOD OF MAKING THE SAME - A backside illuminated image sensor includes a substrate with a substrate depth, where the substrate includes a pixel region and a peripheral region. The substrate further includes a front surface and a back surface. The backside illuminated image sensor includes a first isolation structure formed in the pixel region of the substrate, where a bottom of the first isolation structure is exposed at the back surface of the substrate. The backside illuminated image sensor includes a second isolation structure formed in the peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. The backside illuminated image sensor includes an implant region adjacent to at least a portion of sidewalls of each isolation structure in the pixel region. | 06-05-2014 |
| 20150111334 | METHOD OF MAKING BACKSIDE ILLUMINATED IMAGE SENSORS - A method of making a backside illuminated image sensor includes forming a first isolation structure in a pixel region of a substrate, where a bottom of the first isolation structure is exposed at a back surface of the substrate. The method further includes forming a second isolation structure in a peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. Additionally, the method includes forming an implant region adjacent to at least a portion of sidewalls of the first isolation structure, where the portion of the sidewalls is located closer to the back surface than a front surface of the substrate, and where the second isolation structure is free of the implant region. | 04-23-2015 |
| Patent application number | Description | Published |
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| 20130210190 | APPARATUS AND METHOD FOR PRODUCING SOLAR CELLS - A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces wherein each of the plurality of surfaces are disposed facing an interior surface of the vacuum chamber. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is disposed in a first subchamber of the vacuum chamber and configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. A first isolation source is configured to isolate the evaporation source from the first sputtering source. | 08-15-2013 |
| 20140131193 | APPARATUS AND METHOD FOR FORMING THIN FILMS IN SOLAR CELLS - Apparatus for forming a solar cell comprises a housing defining a chamber including a substrate support. A sputtering source is configured to deposit particles of a first type over at least a portion of a surface of a substrate on the substrate support. An evaporation source is configured to deposit a plurality of particles of a second type over the portion of the surface of the substrate. A cooling unit is provided between the sputtering source and the evaporation source. A control system is provided for controlling the evaporation source based on a rate of mass flux emitted by the evaporation source. | 05-15-2014 |
| 20140131198 | SOLAR CELL FORMATION APPARATUS AND METHOD - Apparatuses for forming material films on a solar cell substrate of substantially uniform thickness and processes for forming the same are disclosed. The process performed in the apparatuses is physical vapor deposition (PVD) in some embodiments. In one embodiment, an apparatus includes a specially configured flow aperture. In another embodiment, an apparatus includes moveable shutters which open and close in synchronization with a rotating drum on which substrates are mounted for processing. In other embodiments, the apparatus includes a variable power supply or drum speed control which automatically vary the power supply to the apparatus or drum speed respectively in synchronization with the rotating drum. | 05-15-2014 |
| 20140193939 | METHOD AND SYSTEM FOR FORMING ABSORBER LAYER ON METAL COATED GLASS FOR PHOTOVOLTAIC DEVICES - An apparatus for forming a solar cell includes a housing defining a vacuum chamber, a rotatable substrate support, at least one inner heater and at least one outer heater. The substrate support is inside the vacuum chamber configured to hold a substrate. The at least one inner heater is between a center of the vacuum chamber and the substrate support, and is configured to heat a back surface of a substrate on the substrate support. The at least one outer heater is between an outer surface of the vacuum chamber and the substrate support, and is configured to heat a front surface of a substrate on the substrate support. | 07-10-2014 |
| 20140302634 | APPARATUS AND METHOD FOR PRODUCING SOLAR CELLS - A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. | 10-09-2014 |
| 20150221811 | METHOD AND SYSTEM FOR FORMING ABSORBER LAYER ON METAL COTAED GLASS FOR PHOTOVOLTAIC DEVICES - An apparatus for forming a solar cell includes a housing defining a vacuum chamber, a rotatable substrate support, at least one inner heater and at least one outer heater. The substrate support is inside the vacuum chamber configured to hold a substrate. The at least one inner heater is between a center of the vacuum chamber and the substrate support, and is configured to heat a back surface of a substrate on the substrate support. The at least one outer heater is between an outer surface of the vacuum chamber and the substrate support, and is configured to heat a front surface of a substrate on the substrate support. | 08-06-2015 |
