Patent application number | Description | Published |
20080213951 | Method of fabricating pixel structure - A method of fabricating a pixel structure including the following procedures is provided. First, a substrate having an active device thereon is provided. A patterned passivation layer is formed on the substrate and the active device, and the patterned passivation layer exposes a portion of the active device. Then, a conductive layer is formed over the patterned passivation layer, and the conductive layer is electrically connected to the active device. A mask exposing a portion of the conductive layer is provided above the conductive layer. A laser is used to irradiate the conductive layer via the mask to remove the portion of the conductive layer exposed by the mask. As a result, the remained portion of the conductive layer constitutes a pixel electrode, and the pixel electrode is electrically connected to the active device. The method simplifies the fabrication process of a pixel structure, and thus reduces the fabrication cost. | 09-04-2008 |
20080227252 | FABRICATION METHODS OF THIN FILM TRANSISTOR SUBSTRATES - Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost. | 09-18-2008 |
20090053844 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is provided. A substrate having a gate thereon is provided. Next, a gate dielectric layer is formed to cover the gate. A channel layer is formed on the gate dielectric layer above the gate. A source and a drain are formed on the channel layer at two sides of the gate, wherein the gate, the channel layer, the source and the drain constitute a thin film transistor (TFT). A passivation layer is formed on the gate dielectric layer and the TFT. A first shadow mask exposing parts of the passivation layer is provided thereabove. The drain is exposed by a laser applied via the first shadow mask to partially remove the passivation layer. A conductive layer is formed to cover the passivation layer and the drain. The conductive layer is then automatically patterned by the patterned passivation layer to form a pixel electrode. | 02-26-2009 |
20090053861 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is provided. A substrate is provided, and a gate is formed on the substrate. A gate dielectric layer covering the gate is formed on the substrate. A semiconductor layer is formed on the gate dielectric layer. A first shadow mask exposing parts of the semiconductor layer is provided above the semiconductor layer. A laser is irradiated on the semiconductor layer through the first shadow mask to remove parts of semiconductor layer and form a channel layer. A source and a drain are respectively formed on the channel layer at both sides of the gate. A patterned passivation layer which covers the channel layer and exposes the drain is formed. A conductive layer is formed to cover the patterned passivation layer and the drain. The conductive layer is automatically patterned by the patterned passivation layer to form a pixel electrode. | 02-26-2009 |
20090068777 | METHOD FOR MANUFACTURING PIXEL STRUCTURE - A method for manufacturing a pixel structure is provided. First, a substrate with a gate formed thereon is provided. Next, a gate dielectric layer covering the gate is formed on the substrate. Then, a channel layer, a source and a drain are formed on the gate dielectric layer over the gate. The source and the drain are disposed on a portion of the channel layer. The gate, the channel layer, the source and the drain constitute a thin film transistor. Then, a passivation layer is formed on the gate dielectric layer and the thin film transistor. After that, a laser beam is utilized to irradiate the passivation layer via a first shadow mask so as to remove a portion of the passivation layer for exposing the drain. Then, a pixel electrode is formed on the gate dielectric layer and connected to the exposed drain. | 03-12-2009 |
20090087954 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost. | 04-02-2009 |
20090104722 | METHOD FOR MANUFACTURING PIXEL STRUCTURE - A method for manufacturing a pixel structure includes providing a substrate having an active device thereon and forming a dielectric layer covering the active device. The dielectric layer has a contact hole disposed over the active device. Next, a first photoresist layer is formed on the dielectric layer over the active device, and a transparent conductive layer is formed to cover a portion of the dielectric layer and the first photoresist layer. The transparent conductive layer is electrically connected to the active device via the contact hole. Besides, the transparent conductive layer is irradiated with use of a laser beam, and a portion of the transparent conductive layer on the first photoresist layer is removed, such that the other portion of the transparent conductive layer on the portion of the dielectric layer forms a pixel electrode. The first patterned photoresist layer is then removed. | 04-23-2009 |
20090108270 | MASTER, PIXEL ARRAY SUBSTRATE, ELECTRO-OPTICAL DEVICE AND METHODS OF MANUFACTURING THE SAME - A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate. | 04-30-2009 |
20090148972 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed. | 06-11-2009 |
20090148987 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain. | 06-11-2009 |
20100197083 | FABRICATION METHODS OF THIN FILM TRANSISTOR SUBSTRATES - Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost. | 08-05-2010 |
20100220082 | Shift Register with Embedded Bidirectional Scanning Function - The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively. | 09-02-2010 |
20100301345 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased. | 12-02-2010 |
20100315569 | PIXEL DESIGNS OF IMPROVING THE APERTURE RATIO IN AN LCD - This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode. | 12-16-2010 |
20100315583 | PIXEL DESIGNS OF IMPROVING THE APERTURE RATIO IN AN LCD - This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line. | 12-16-2010 |
20110096019 | TOUCH PANEL AND TOUCH DISPLAY DEVICE - A touch panel and a touch display device are provided. The touch panel includes a first substrate having an inner surface and an outer surface. A position sensing structure is disposed over the inner surface or the outer surface of the first substrate. A second substrate is disposed opposite to the first substrate, facing the inner surface of the first substrate. A plurality of press sensing structures is disposed between the first and the second substrates and a press signal connecting line is disposed to serially connect all of the press sensing structures. The touch display device includes the above mentioned touch panel. | 04-28-2011 |
20110286571 | SHIFT REGISTER WITH EMBEDDED BIDIRECTIONAL SCANNING FUNCTION - The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively. | 11-24-2011 |
20120100653 | METHODS OF MANUFACTURING MASTER, PIXEL ARRAY SUBSTRATE AND ELECTRO-OPTICAL DEVICE - A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate. | 04-26-2012 |
20120193629 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased. | 08-02-2012 |
20120196392 | PIXEL DESIGNS OF IMPROVING THE APERTURE RATIO IN AN LCD - In one aspect of this invention, a pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode. | 08-02-2012 |