Patent application number | Description | Published |
20090069046 | VIRTUAL PAPER READING DEVICE - A virtual paper reading device comprises a virtual paper reading device for viewing a document from a screen through a mobile device; wherein the document to be read has a size as an original size and an original printed page; a 3 axial sensor in the mobile device for sensing moving direction of the mobile device; a key set for adjusting a size of the document to be presented and a present area of the document to be presented; and an application software for receiving the moving direction message from the 3 axial sensor and adjusting signals from the key set so as to adjust a present area and a size of the document to be presented on the screen of the mobile device. The user can read the message from the document easily and conveniently. | 03-12-2009 |
20110042781 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region. | 02-24-2011 |
20110042804 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions. | 02-24-2011 |
20110042807 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions. | 02-24-2011 |
20110079903 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer. | 04-07-2011 |
20110193210 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad. | 08-11-2011 |
20110317371 | ELECTRONIC COMPONENT PACKAGE AND FABRICATION METHOD THEREOF - An electronic component package is described. The electronic component package includes a first electronic component package module mounted on a surface of a packaging layer. A second electronic component package module laminated on a bottom of the first electronic component package module is mounted on a surface of a packaging layer. The first and second electronic component package modules respectively include at least two semiconductor chips laminated. A first redistribution layer is between the first and the second electronic component package modules, electrically connected to the first and the second electronic component package modules. A conductive bump is mounted on a bottom of the second electronic component package module, electrically connected to the second electronic component package module. | 12-29-2011 |
20120280389 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate. | 11-08-2012 |