Patent application number | Description | Published |
20080217172 | Apparatus For Measuring Electrochemical Corrosion - Disclosed herein is an electrochemical corrosion sensor. The sensor may include an array of electrodes wherein each electrode may include a diamond like carbon coating disposed on at least a portion of the electrodes. The coating thickness may be at least about 1 micron. The electrodes may therefore provide relatively more accurate determination of electrode corrosion rates that may be more consistent with coupon type gravimetric testing. | 09-11-2008 |
20090045047 | Conformal Magnetron Sputter Deposition - An apparatus and method for magnetron sputter coating of an interior surface of a hollow substrate defining at least one irregular contour. The apparatus may contain a vacuum chamber and a target containing one or more metals having an exterior surface defining at least one irregular contour. The exterior surface of the target may be configured to conform to at least a portion of an irregular contour of the interior surface of the hollow substrate to be coated. A magnet assembly may be supplied which may include a plurality of magnets where the magnets are positioned substantially within a metallic target alloy. | 02-19-2009 |
20100224913 | One-dimensional FET-based corrosion sensor and method of making same - A field effect transistor corrosion sensor ( | 09-09-2010 |
20120043981 | Corrosion Monitoring of Concrete Reinforcement Bars (Or Other Buried Corrodable Structures) Using Distributed Node Electrodes - Systems and methods for real time detection of corrosion of rebars embedded in a concrete structure. Test bars are selected for corrosion testing purposes, and may or may not also be part of the concrete reinforcement structure. These test bars are coated, and exposed sections of these test bars form a network of node electrodes. Electrical measurement from a counter electrode near a node electrode provides an indication of corrosion at that node electrode. Using a system of node electrodes and counter electrodes, a large concrete area may be monitored, and if corrosion is indicated, a methodical selection of electrodes can be used to locate the corrosion. The same concepts may be applied to detect corrosion in buried structures, such as pipelines and tanks. | 02-23-2012 |
Patent application number | Description | Published |
20110153931 | HYBRID STORAGE SUBSYSTEM WITH MIXED PLACEMENT OF FILE CONTENTS - A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD. | 06-23-2011 |
20120066688 | PROCESSOR THREAD LOAD BALANCING MANAGER - An operating system of an information handling system (IHS) determines a process tree of data sharing threads in an application that the IHS executes. A load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS). | 03-15-2012 |
20120198121 | METHOD AND APPARATUS FOR MINIMIZING CACHE CONFLICT MISSES - A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set. | 08-02-2012 |
20120198187 | Technique for preserving memory affinity in a non-uniform memory access data processing system - Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented. | 08-02-2012 |
20120204188 | PROCESSOR THREAD LOAD BALANCING MANAGER - A processor thread load balancing manager employs an operating system of an information handling system (IHS) that determines a process tree of data sharing threads in an application that the IHS executes. The load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS). | 08-09-2012 |
20120221812 | METHOD FOR PRESERVING MEMORY AFFINITY IN A NON-UNIFORM MEMORY ACCESS DATA PROCESSING SYSTEM - A method for preserving memory affinity in a computer system is disclosed. The method reduces and sometimes eliminates memory affinity loss due to process migration by restoring the proper memory affinity through dynamic page migration. The memory affinity access patterns of individual pages are tracked continuously. If a particular page is found almost always to be accessed from a particular remote access affinity domain for a certain number of times, and without any intervening requests from other access affinity domain, the page will migrate to that particular remote affinity domain so that the subsequent memory access becomes local memory access. As a result, the proper pages are migrated to increase memory affinity. | 08-30-2012 |
20130218892 | HYBRID STORAGE SUBSYSTEM WITH MIXED PLACEMENT OF FILE CONTENTS - A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD. | 08-22-2013 |
20140095791 | PERFORMANCE-DRIVEN CACHE LINE MEMORY ACCESS - According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied. | 04-03-2014 |
20140095796 | PERFORMANCE-DRIVEN CACHE LINE MEMORY ACCESS - According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied. | 04-03-2014 |
20150254113 | Lock Spin Wait Operation for Multi-Threaded Applications in a Multi-Core Computing Environment - A method, system and computer-usable medium are disclosed for a lock-spin-wait operation for managing multi-threaded applications in a multi-core computing environment. A target processor core, referred to as a “spin-wait core” (SAC), is assigned (or reserved) for primarily running spin-waiting threads. Threads operating in the multi-core computing environment that are identified as spin-waiting are then moved to a run queue associated with the SAC to acquire a lock. The spin-waiting threads are then allocated a lock response time that is less than the default lock response time of the operating system (OS) associated with the SAC. If a spin-waiting fails to acquire a lock within the allocated lock response time, the SAC is relinquished, ceding its availability for other spin-waiting threads in the run queue to acquire a lock. Once a spin-waiting thread acquires a lock, it is migrated to its original, or an available, processor core. | 09-10-2015 |
Patent application number | Description | Published |
20080222227 | Design Structure for a Booth Decoder - A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation. | 09-11-2008 |
20080303553 | METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER - A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate. | 12-11-2008 |
20080303554 | STRUCTURE FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER - A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate. | 12-11-2008 |
20090013022 | Multiplier Engine Apparatus and Method - A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit | 01-08-2009 |
20090072863 | Transmission Gate Multiplexer - A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer. | 03-19-2009 |
20090096486 | Structure for Transmission Gate Multiplexer - A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer. | 04-16-2009 |
Patent application number | Description | Published |
20100041919 | PROCESS AND APPARATUS FOR RECOVERY OF ACETIC ACID FROM METHYL ACETATE - An apparatus and process are described for recovery of a carboxylic acid by hydrolysis of an ester in a mixture comprising the ester, an alcohol and water. The apparatus comprises a catalytic distillation column containing an acidic catalyst and a distillation column. Simultaneously and interdependently the alcohol is catalytically dehydrated to the corresponding ether and water, and said water reacts with the ester to generate a carboxylic acid rich stream from the catalytic distillation column. The acid is recovered by distillation in the distillation column. The process requires no added water. A second embodiment of the apparatus and process has means to co-feed one or both of added methanol and/or water with the feed to maintain substantially optimum operation independent of feed composition. | 02-18-2010 |
20130277200 | SPRING LOADED PRESSURE RELIEF DEVICE - A pressure relief device for preventing damage to a tray in a distillation column arising from sudden pressure surges includes a plate normally closing an opening in the tray, a frame above which the tray can move vertically, and at least one spring assembly connecting the plate to the frame. When there is a pressure surge, the plate moves vertically to open the pressure relief device. When the pressure differential between zones above and below the plate has been relieved, the spring assembly returns the pressure relief device to the closed position in which the plate is coplanar with the fixed tray. | 10-24-2013 |
20140378703 | Process for recovery of a carboxylic acid from a feed stream containing the corresponding ester - A carboxylic acid e.g. acetic acid, is recovered from an aqueous feed stream containing the corresponding ester, an alcohol and a small amount of water by catalytically dehydrating the alcohol to the corresponding ether and water, and reacting the water with the ester to generate a liquid carboxylic acid rich product stream. The acid is recovered by distillation. In a second embodiment, additional alcohol and/or water are co-fed with the feed or fed directly to a catalytic distillation column, resulting in a liquid bottom product stream of substantially pure acetic acid and a top distillate stream of substantially pure ether. | 12-25-2014 |