Patent application number | Description | Published |
20090021999 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter. | 01-22-2009 |
20090201757 | SEMICONDUCTOR DEVICE - Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh. | 08-13-2009 |
20100054035 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array | 03-04-2010 |
20100090675 | Semiconductor device and test method therefor - Disclosed is a semiconductor device including internal power supply generating circuits for generating internal power supplies and data terminals via which data signals are output or input/output. The internal power supply monitor terminals are in common use with the data terminals. The semiconductor device also includes selection circuits for selecting, by a test control signal, whether or not output voltages of the internal power supply generating circuits are to be output to the data terminals. | 04-15-2010 |
20100124139 | SEMICONDUCTOR DEVICE INCLUDING AN ANTI-FUSE ELEMENT - A semiconductor device includes a first high potential power supply, a second low potential power supply, a third power supply having a potential higher than the first, a fourth power supply having a potential more negative than the second, and an anti-fuse element having a node at each end, one of which is connected to the fourth power supply. A driver transistor has a source connected to the third power supply, a gate connected to a control node and a drain connected to one end of the anti-fuse element. A decoding circuit includes a load transistor connected between the third power supply and the control node and at least one selection transistor connected between the second power supply and the control node. A decision circuit is connected to the first and second power supplies. The decision circuit decides the resistance value of the anti-fuse element. The anti-fuse element is rendered electrically conductive in response to activation of the driver transistor as selected by the decoding circuit. The decision circuit decides whether or not the anti-fuse element has been rendered electrically conductive. | 05-20-2010 |
20110058401 | Semiconductor memory device having pad electrodes arranged in plural rows - To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area. | 03-10-2011 |
20110063927 | Semiconductor device using plural internal operation voltages and data processing system using the same - A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address signal output from the level shifter, address decoders that generate a decode signal by decoding the address signal output from the address controller, and level shifters that convert an amplitude of the address signal or of the decode signal from the second amplitude to the first amplitude such that at least an amplitude level of the decode signal becomes the first amplitude. | 03-17-2011 |
20110303988 | Semiconductor device and level shift circuit using the same - A level shift circuit includes: a pair of first and second P-channel transistors which are connected in a flip-flop manner and whose sources connected to a first power supply line; a pair of first and second N-channel transistors with the first N-channel transistor provided between the first P-channel transistor and a second power supply line and the second N-channel transistor provided between the second P-channel transistor and the second power supply line, in which input signals complementary to each other are inputted to their gates; and a current supply circuit provided between the first power supply line and a drain of the first N-channel transistor and between the first power supply line and a drain of the second N-channel transistor, respectively. The current supply circuit includes third and fourth N-channel transistors with their sources connected to drains of the first and second N-channel transistors and third and fourth P-channel transistors serving as current limiting elements with their one ends connected to the first power supply line and the other ends connected to drains of the third and fourth P-channel transistors. | 12-15-2011 |
20130082735 | LOGIC CIRCUIT PERFORMING EXCLUSIVE OR OPERATION AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a logic circuit that includes a transistor T | 04-04-2013 |
20130082736 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE-INPUT LOGIC CIRCUIT WITH OPERATION RATE BALANCED WITH DRIVING ABILITY - A device includes first through third logic circuits. Each of first and second logic circuits includes a first circuit portion generating a first output signal in response to a first input signal when a second input signal takes a first logic level, and a second circuit portion transferring the first input signal to output the first output signal when the second input signal takes a second logic level. The third logic circuit includes a third circuit portion generating a second output signal in response to the first output signal supplied from the first logic circuit when the first output signal supplied from the second logic circuit takes a third logic level, and a fourth circuit portion generating the second output signal in response to the first output signal supplied with the first logic circuit when the first output signal supplied from the second logic circuit takes a fourth logic level. | 04-04-2013 |
20130082737 | SEMICONDUCTOR DEVICE HAVING SERIALIZER CONVERTING PARALLEL DATA INTO SERIAL DATA TO OUTPUT SERIAL DATA FROM OUTPUT BUFFER CIRCUIT - Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2 n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 04-04-2013 |
20130082758 | SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER CIRCUIT IN WHICH IMPEDANCE THEREOF CAN BE CONTROLLED - Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 04-04-2013 |
20130091327 | SEMICONDUCTOR DEVICE PERFORMING BURST ORDER CONTROL AND DATA BUS INVERSION - Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits. | 04-11-2013 |
20130094321 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER TO CONTROL OUTPUT TIMING OF DATA AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage. | 04-18-2013 |