Patent application number | Description | Published |
20080270969 | METHOD FOR CORRECTING PHOTOMASK PATTERN - A method for correcting a photomask pattern is provided. The correcting method performs a verification of a focus-exposure matrix (FEM) and an overlay variation on a layout area having contact holes or vias in a layout pattern so as to generate a hint information. The layout pattern of the photomask is corrected according to the hint information to prevent the contact holes or vias from being exposed in arrangement to corresponding metal layer, poly layer, or diffusion layer. | 10-30-2008 |
20130157178 | METHOD FOR CORRECTING LAYOUT PATTERN AND METHOD FOR MANUFACTURING PHOTOMASK - A method for correcting a layout pattern includes the following steps. A first layout pattern, a second layout pattern, and a mis-alignment value are provided. The first layout pattern includes a first conducting line pattern, and the second layout pattern includes at least one contact via pattern. The contact via pattern at least partially overlaps the first conducting line pattern. The layout pattern is verified whether spacing between the contact via pattern and the first conducting line pattern is smaller than the mis-alignment value by a computing system. A first modified contact via pattern is then obtained by expanding the contact via pattern along a direction away from the spacing smaller than the mis-alignment value. | 06-20-2013 |
20140093814 | METHOD FOR FORMING PHOTOMASKS - A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer. | 04-03-2014 |
20140220482 | METHOD FOR FORMING PATTERNS - A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer. | 08-07-2014 |
20140241027 | Static random access memory unit cell structure and static random access memory unit cell layout structure - A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided. | 08-28-2014 |
20140256132 | METHOD FOR PATTERNING SEMICONDUCTOR STRUCTURE - A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask. | 09-11-2014 |
20140282295 | Method for Forming Photo-masks and OPC Method - The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method. | 09-18-2014 |
20150052491 | METHOD FOR GENERATING LAYOUT PATTERN - A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns. | 02-19-2015 |
20150072272 | Method For Forming Photo-Mask And OPC Method - A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method. | 03-12-2015 |