Patent application number | Description | Published |
20110074737 | Method and Device for Adjusting Brightness of an Optical Touch Panel - A method and device are provided for adjusting brightness of an optical touch panel. The optical touch panel comprises a microprocessor, a display module including a back light source, and an optical position detection device including optical transmitting devices and optical receiving devices. The method comprises detecting, via the optical receiving devices, a current ambient light level on the display module. The method further comprises generating, via the optical receiving devices, a current ambient light level signal indicative of the current ambient light level and transmitting the current ambient light level signal to the microprocessor. Furthermore, the method comprises adjusting, via the microprocessor, brightness of the back light source based on the current ambient light level signal. | 03-31-2011 |
20130227199 | FLASH MEMORY STORAGE SYSTEM AND ACCESS METHOD - The present disclosure relates, according to some embodiments, to a data writing method in a storage system. The method comprises receiving data by the storage media controller, reading a non-volatile memory operation mode in the memory unit by a central control unit, in which the mode corresponds to a data reliability lower than the data reliability requirement of the storage system, reading a data reliability reduction condition in the memory unit by the central control unit, determining whether a system information related to the data meets the condition by the central control unit, and controlling the media control unit to write the data into the non-volatile memory according to the mode by the central control unit when the system information meets the condition. | 08-29-2013 |
20140312783 | ADJUSTING BRIGHTNESS OF AN OPTICAL TOUCH PANEL - A method, device, and computer program product are provided for adjusting brightness of an optical touch panel. The optical touch panel comprises a microprocessor, a display module including a back light source, and an optical position detection device including optical transmitting devices and optical receiving devices. The method comprises detecting, via the optical receiving devices, a current ambient light level on the display module. The method further comprises generating, via the optical receiving devices, a current ambient light level signal indicative of the detected current ambient light level and transmitting the current ambient light level signal to the microprocessor. Furthermore, the method comprises adjusting, via the microprocessor, brightness of the back light source based on the current ambient light level signal. | 10-23-2014 |
Patent application number | Description | Published |
20080306738 | VOICE PROCESSING METHODS AND SYSTEMS - Voice processing methods and systems are provided. An utterance is received. The utterance is compared with teaching materials according to at least one matching algorithm to obtain a plurality of matching values corresponding to a plurality of voice units of the utterance. Respective voice units are scored in at least one first scoring item according to the matching values and a personified voice scoring algorithm. The personified voice scoring algorithm is generated according to training utterances corresponding to at least one training sentence in a phonetic-balanced sentence set of a plurality of learners and at least one real teacher, and scores corresponding to the respective voice units of the training utterances of the learners in the first scoring item provided by the real teacher. | 12-11-2008 |
20120111971 | OUTDOOR SHOWER DEVICE - An outdoor shower device, comprising a water storage module, a power supply module, a heating module, a control module, a water supply module and an alarm module, wherein the water storage module is employed for water source storage, the control module controls the heating module to heat the water based on the water temperature, and then the water supply module provides the heated water for use. Furthermore, the power supply module provides electric power required for integral operations and enables the alarm module to determine the water level; in case the water level is exceedingly low, it is possible to present blinking display signal and audio alarm sound to inform the user of such a low water level thereby allowing the user to more effectively apply the outdoor shower device of the present invention. | 05-10-2012 |
Patent application number | Description | Published |
20080309365 | Method for Determining Time Dependent Dielectric Breakdown - The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage. | 12-18-2008 |
20080318378 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 12-25-2008 |
20110010117 | APPARATUS FOR NBTI PREDICTION - An apparatus comprises a circuit for measuring a gate leakage current of a plurality of transistors. A circuit is provided to apply heat to gates of the plurality of transistors. A circuit is provided to apply a single stress bias voltage to the plurality of transistors for a stress period t. The stress bias voltage is sufficient to cause a 10% degradation in a drive current of the transistor within the stress period t. A processor is provided for estimating a negative bias temperature instability (NBTI) lifetime τ of the transistor based on a relationship between the gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors. The relationship is determined from data observed while applying the single stress bias voltage. | 01-13-2011 |
Patent application number | Description | Published |
20100148679 | CURRENT-BALANCE CIRCUIT AND BACKLIGHT MODULE HAVING THE SAME - The present invention relates to a current-balance circuit and a backlight module having the same. The current balance circuit includes a current balance unit, a control unit, and a detection unit. The current balance unit is connected to a plurality of light units to regulate the current of the plurality of light units, independent from the effects of input voltage. The detection unit is connected to the plurality of light units and the current balance unit to detect the minimum operating voltage for the plurality of light units. The control unit, connected to the current balance unit, controls the operation of the plurality of light units. | 06-17-2010 |
20100149221 | DRIVE CURRENT OF LIGHT SOURCE BY COLOR SEQUENTIAL METHOD - The present invention relates to a drive circuit of light source by color sequential method for generating a full-color image based on sequential switching between red, green and blue illuminations. The drive circuit of light source by color sequential method includes a color-sequential control circuit and a plurality of radiating areas coupled to multiple light units. The color-sequential control circuit is connected to those radiating areas to control the operation thereof by the color sequential method. | 06-17-2010 |
20110096084 | LIQUID CRYSTAL DISPLAY WITH FUNCTION OF STATIC COLOR COMPENSATION AND METHOD THEREOF - The present invention discloses a liquid crystal display with function of static color compensation and method thereof, the purpose of the present invention is achieved by utilizing LC Off technique and light sensing technique. The liquid crystal display comprises: a liquid crystal plate; a backlight, disposed on at least one side of the liquid crystal plate; at least one light sensor, disposed adjacent to the liquid crystal plate, and the light sensor has a sensing plane which faces to the backlight; and a timing controller, which receives brightness value measured from the light sensor when LC Off and computes the data to monitor the brightness and chromaticity of the backlight. | 04-28-2011 |
Patent application number | Description | Published |
20100127672 | Power Supply Device with Fast Output Voltage Switching Capability - A power supply device is disclosed in the present invention, which includes a DC-DC boost converter and a charge recycling circuit. The DC-DC boost converter is utilized for boosting an input voltage to generate an output voltage, and adjusting a voltage level of the output voltage according to a level switching signal. The charge recycling circuit is electrically connected to the DC-DC boost converter, and is utilized for generating a current path according to the level switching signal to recycle redundant charges from the DC-DC boost converter when the output voltage is switched from high to low and to return stored charges back to the DC-DC boost converter when the output voltage is switched from low to high, so as to accelerate voltage switching of the output voltage and to reduce power consumption of the DC-DC boost converter. | 05-27-2010 |
20100164855 | Backlight Control Method for Liquid Crystal Panel and Related Liquid Crystal Display - A backlight control method for an LCD panel is disclosed, and includes steps of dividing the LCD panel into a plurality of backlight areas; configuring an expanding area and a weighted area for each backlight area of the plurality of backlight areas; and determining backlight intensity of each backlight area according to a weighted average grayscale value calculated with all pixels inside the expanding area and the weighted area, wherein the expanding area is formed by expanding outwardly from each backlight area, and the weighted area is focused on the center of each backlight area and has a range not greater than that of the expanding area. | 07-01-2010 |
20100264847 | VOLTAGE CONVERTER, BACKLIGHT MODULE CONTROL SYSTEM AND CONTROL METHOD THEREOF - A backlight module control system includes a plurality of backlight sub-modules, a control signals output unit, a voltage converter and a plurality of current control units. The control signals output circuit is for providing a voltage control signal, a current control signal and a plurality of PWM signals; the voltage converter is coupled to the control signals output circuit and the backlight sub-modules, and is for outputting an output voltage to the backlight sub-modules according to the voltage control signal; the current control units are coupled to the backlight sub-modules, respectively, and each current control unit is for determining a current of its corresponding backlight sub-module according to the current control signal, and each current control unit is further utilized for determining whether its corresponding backlight sub-module is enabled or not according to its corresponding PWM signal. In addition, only one backlight module is enabled at a same time. | 10-21-2010 |
Patent application number | Description | Published |
20150325453 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer. | 11-12-2015 |
20160064528 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and a hard mask atop the metal gate; and performing a high-density plasma (HDP) process to form a cap layer on the hard mask and the substrate. | 03-03-2016 |
20160071944 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other. | 03-10-2016 |
20160104645 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures. | 04-14-2016 |
Patent application number | Description | Published |
20100295852 | GRAPHICS PROCESSING SYSTEM WITH POWER-GATING CONTROL FUNCTION, POWER-GATING CONTROL METHOD, AND COMPUTER PROGRAM PRODUCTS THEREOF - The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders. | 11-25-2010 |
20150043274 | MEMORY WITH MULTIPLE LEVELS OF DATA RETENTION - A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode. | 02-12-2015 |
20150085589 | DATA MOVEMENT IN MEMORY DEVICES - Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed. | 03-26-2015 |
20150149867 | STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data. | 05-28-2015 |
20150280742 | CACHING METHOD AND DATA STORAGE SYSTEM CAPABLE OF PROLONGING SERVICE LIFETIME OF A CACHE MEMORY - In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache memory. The codeword includes a data portion, a checksum parity portion and an error correction code (ECC) parity portion. In response to a read request for the user data, the codeword read from the cache memory is decoded based on the ECC parity portion to correct one or more bit errors within the data portion so as to generate a read data portion and a read checksum parity portion. Upon identifying that a validating checksum portion generated based on the read data portion matches the read checksum parity portion, the read data portion serving as the user data is outputted. Otherwise, a data storage unit outputs the user data previously stored therein. | 10-01-2015 |
Patent application number | Description | Published |
20100052066 | STRUCTURE AND METHOD FOR A CMOS DEVICE WITH DOPED CONDUCTING METAL OXIDE AS THE GATE ELECTRODE - A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer. | 03-04-2010 |
20110198721 | METHOD FOR THINNING A WAFER - A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs. | 08-18-2011 |
20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
20120261827 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 10-18-2012 |
20130126946 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask. | 05-23-2013 |
20130147057 | THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT - Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in | 06-13-2013 |
20130193578 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 08-01-2013 |
20130302979 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS - A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate. | 11-14-2013 |
20140015146 | SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. | 01-16-2014 |
20140087505 | Light-Emitting Diodes on Concave Texture Substrate - A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency. | 03-27-2014 |
20140235001 | Reflective Layer for Light-Emitting Diodes - A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is preferably located lower than the active layer of the individual LEDs. | 08-21-2014 |
20150147834 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 05-28-2015 |
20160064632 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a substrate; a plurality of light-emitting diodes formed on the substrate, wherein each of the plurality of light-emitting diodes comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting diodes; and a top electrode formed on the reflective layer and the plurality of light-emitting diodes. | 03-03-2016 |