Patent application number | Description | Published |
20090306640 | Vein Therapy Device and Method - A vapor delivery and insulation device is provided that may include any of a number of features. One feature of the device is that it can deliver vapor to the veins of a patient. The vapor can be generated within the device, in a handle of the device, or external to the device. Another feature of the device is that it can actively insulate the vapor to minimize heat transfer from a vapor delivery lumen of the device to an exterior surface of the device. The active insulation can be a vacuum or a flowing gas. Methods associated with use of the device are also covered. | 12-10-2009 |
20110178584 | VAGINAL REMODELING DEVICE AND METHODS - This invention relates generally to apparatus and methods for tightening tissue of the female genitalia by heating targeted connective tissue with radiant energy, while cooling the mucosal epithelial surface over the target tissue to protect it from the heat. Embodiments include a handle and treatment tip that has both an energy delivery element and a cooling mechanism. The handle may be a two-handed handle allowing control even while rotating and maneuvering the treatment around the genital opening. The apparatus or system may also include an integrated controller, which may confirm tissue contact without applying RF energy, based only on the temperature of the applicator and the time since the last application of energy from the applicator. | 07-21-2011 |
20110264176 | HOT TIP VEIN THERAPY DEVICE - Methods and apparatus for generating vapor within a catheter are provided which may include any number of features. One feature is generating vapor with an electrode array within a catheter. Another feature is sensing an impedance of the electrode array, and adjusting the power delivered to the electrode array to fully generate vapor within the catheter. Another feature is delivering the vapor to a vein of a patient for vein reduction therapy. | 10-27-2011 |
20130123888 | HOT TIP LASER GENERATED VAPOR VEIN THERAPY DEVICE - Methods and apparatus for generating vapor within a catheter are provided which may include any number of features. One feature is generating vapor with a fiber optic, laser fiber optic, or fiber optic bundle within a catheter. Another feature is sensing a temperature of the fiber optic, and adjusting the power delivered to the electrode array to fully generate vapor within the catheter. Another feature is delivering the vapor to a vein of a patient for vein reduction therapy. | 05-16-2013 |
Patent application number | Description | Published |
20090061087 | COMBINATORIAL PROCESS SYSTEM - A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate. | 03-05-2009 |
20090061108 | COMBINATORIAL PROCESS SYSTEM - A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate. | 03-05-2009 |
20090069924 | COMBINATORIAL PROCESS SYSTEM - A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate. | 03-12-2009 |
Patent application number | Description | Published |
20090073977 | ROUTING TRAFFIC THROUGH A VIRTUAL ROUTER-BASED NETWORK SWITCH - Methods and systems are provided for routing traffic through a virtual router-based network switch. According to one embodiment, a flow data structure is established that identifies current packet flows associated with multiple virtual routers in the virtual router-based network device. When an incoming packet is received by the virtual router-based network device, it is then determined whether the incoming packet is associated with a current packet flow by accessing the flow data structure based on a header associated with the incoming packet. If it is determined that the incoming packet is associated with the current packet flow, then the incoming packet is hardware forwarded via a network interface of the virtual router-based network device without intervention by a processor of the virtual router-based network device, otherwise the incoming packet is forwarded to software on the processor for flow learning. | 03-19-2009 |
20090225759 | HIERARCHICAL METERING IN A VIRTUAL ROUTER-BASED NETWORK SWITCH - Methods and systems are provided for applying metering and rate-limiting in a virtual router environment and supporting a hierarchy of metering/rate-limiting contexts per packet flow. According to one embodiment, multiple first level metering options and multiple second level metering options associated with a hierarchy of metering levels are provided. A virtual routing engine receives packets associated with a first packet flow and packets associated with a second packet flow. The virtual routing engine performs a first type of metering of the first level metering options on the packets associated with the first packet flow using a first metering control block (MCB) and performs a second type of metering of the second level metering options on the packets associated with the first packet flow and the packets associated with the second packet flow using a second MCB. | 09-10-2009 |
20110200044 | HARDWARE-ACCELERATED PACKET MULTICASTING IN A VIRTUAL ROUTING SYSTEM - Methods and systems are provided for hardware-accelerated packet multicasting in a virtual routing system. According to one embodiment, a virtual routing engine (VRE) including virtual routing processors and corresponding memory systems are provided. The VRE implements virtual routers (VRs) operable on the virtual routing processors and associated routing contexts utilizing potentially overlapping multicast address spaces resident in the memory systems. Multicasting of multicast flows originated by subscribers of a service provider is simultaneously performed on behalf of the subscribers. A VR is selected to handle multicast packets associated with a multicast flow. A routing context of the VRE is switched to one associated with the VR. A packet of the multicast flow is forwarded to multiple destinations by reading a portion of the packet from a common buffer for each instance of multicasting and applying transform control instructions to the packet for each instance of multicasting. | 08-18-2011 |
20140177631 | HARDWARE-ACCELERATED PACKET MULTICASTING - Methods and systems for hardware-accelerated packet multicasting are provided. According to one embodiment, a multicast packet is received at an ingress system of a packet-forwarding engine (PFE). Multiple flow classification indices are identified for the multicast packet by the ingress system. The multiple flow classification indices are sent to an egress system of the PFE by the ingress system. A single copy of the multicast packet is buffered in a memory accessible by the egress system. Corresponding transform control instructions are identified by the egress system based on each flow classification index. The single copy of the multicast packet is read from the memory. The multicast packet is transformed to an outgoing packet for each instance of the multicast packet based on the corresponding transform control instructions. The outgoing packet is transmitted for routing to a network. | 06-26-2014 |
20150195098 | HARDWARE-ACCELERATED PACKET MULTICASTING - Methods and systems for hardware-accelerated packet multicasting are provided. According to one embodiment, a first packet to be multicast to a first destination and a second packet to be multicast to a second destination are received. The first and second packets are classified in accordance with different virtual routers (VRs) of multiple VRs instantiated by a virtual routing engine (VRE) of a virtual routing system by determining a first selected VR to multicast the first packet and a second selected VR to multicast the second packet. For each of the first and second packets: a routing context of the VRE is switched to a routing context associated with the selected VR; at least a portion of the packet is read from one of multiple multicast address spaces associated with the selected VR; and the packet is forwarded to the destination. | 07-09-2015 |
Patent application number | Description | Published |
20110018556 | PRESSURE AND TOUCH SENSORS ON FLEXIBLE SUBSTRATES FOR TOYS - A capacitive sensor comprises patterned electrodes and printed wires of conductive material integrated with sensing circuits on flexible circuit substrates. The flexible circuit substrates are fingered or otherwise elongated to distribute sensing points to the limbs in a toy doll or animal, or squares on a board game. Such sensing points can detect the presence of a finger even though actual contact is not made by measuring the proportions and changes in stray capacitance attaching to the various electrodes. Touch sensors are therefore possible even when the capacitor sensor's sensing points are covered by a doll's plastic skin or a plush animal's fur. Including an interlayer of open cell foam under the flexible circuit substrate further implements a pressure sensor because applied pressures will deform the geometries of the capacitor electrodes and dielectrics enough to produce a measurable change in capacitance. | 01-27-2011 |
20110021108 | METHOD AND SYSTEM FOR INTERACTIVE TOYS - Toy design methods break down the desired behavior of an electro-mechanical toy into unique states represented with electronics and/or mechanical modeling. The toy will exist in such rest state until some external event acts to trigger a state change in one or more of the parts. Any event can be defined at an appropriate user, environmental, or sensory input to can act as a trigger for the toy to react with some predefined behavior. Each of several physical toy states can be uniquely represented with an electronic circuit register. A multi-bit register status at any one particular instant directly represents the entire state the toy is in, and is quick and simple to inspect and act on. State changes triggered by input stimuli cause a change in the register bits reflecting the changing conditions of the toy. | 01-27-2011 |
20110021109 | TOY AND COMPANION AVATAR ON PORTABLE ELECTRONIC DEVICE - A toy and software application accessory extends the distinguishing play experience of a particular toy to a digital play experience on personal digital assistant, personal navigation device, or other electronic device like an iPod or iphone with an accelerometer, speaker, and a touch-sensitive display screen. The software application accessory creates a digital play experience or video game on the electronic device that presents avatars, dialog, and backgrounds that convincingly accessorize the physical toy. Wireless connectivity to a PC and the Internet allows the toy or the electronic device to download updates, modifications, and enhancements to its basic program. New personalities can be downloaded that change the toy play experience, and extend the play life of the toy by introducing new and creative play experiences. A personality accessory kit includes the new personalities, clothes, props, and other matching accessories. | 01-27-2011 |
Patent application number | Description | Published |
20100111537 | Passive Optical Networks with Mode Coupling Receivers - An apparatus comprising a mode coupler configured to couple a plurality optical signals into a plurality of modes, and a receiver coupled to the mode coupler and configured to detect the modes to obtain the optical signals, wherein the optical signals are coupled from single mode fibers. Also disclosed is an apparatus comprising a plurality of single mode waveguides configured to transport a plurality of single mode signals, and a detector coupled to the single mode waveguides and configured to detect the single mode signals, wherein the single mode signals are substantially coupled without loss from the single mode waveguides to the detector. Also disclosed is a method comprising receiving a plurality of single mode optical channels, coupling the single mode optical channels into a multimode channel, and detecting the optical modes corresponding to the channels in the multimode channel. | 05-06-2010 |
20100226649 | Multi-Fiber Ten Gigabit Passive Optical network Optical Line Terminal for Optical Distribution Network Coexistence with Gigabit Passive Optical Network - An apparatus comprising a wavelength division multiplexing (WDM) coupler configured to couple an optical line terminal (OLT) comprising a transmitter and a receiver, wherein the WDM coupler is coupled to the transmitter via a first fiber and to the receiver via a second fiber. An apparatus comprising a WDM coupler for a passive optical network (PON) comprising a plurality of filters and a plurality of ports, wherein the WDM coupler comprises fewer filters than ports. A method comprising receiving a downstream optical signal intended for an optical network terminal (ONT) via a first fiber, and transmitting an upstream optical signal received from the ONT via a second fiber. | 09-09-2010 |
20110091210 | Coupled Seed Light Injection for Wavelength Division Multiplexing Passive Optical Networks - An apparatus comprising a first optical transmitter configured to couple to a second optical transmitter, a first optical receiver, and a seed light source, wherein the first optical transmitter and the first optical receiver are part of a first passive optical network (PON) and the second optical transmitter and a second optical receiver are part of a second PON, and wherein at least one of the first optical transmitter and the second optical transmitter is an injection locked laser transmitter. Also disclosed is a method comprising feeding a seed light to a plurality of injection locked laser transmitters in a plurality of PONs using only one broadband light source (BLS), wherein each PON comprises an optical line terminal (OLT) transmitter and a plurality of optical network units (ONUs) transmitters. | 04-21-2011 |
20110091214 | Cascased Injection Locking of Fabry-Perot Laser for Wave Division Modulated Passive Optical Networks - An optical network unit (ONU) comprising a first optical fiber, a first optical circulator coupled to the first optical fiber, a first seed light injected laser coupled to the first optical circulator, wherein the first optical circulator is positioned between the first seed light injected laser and the first optical fiber, and a second seed light injected laser coupled to the first optical circulator and the first seed light injected laser, wherein the first optical circulator is positioned between the second seed light injected laser and the first optical fiber. Also disclosed is a method comprising receiving a seed light signal, amplifying the seed light signal using seed light injection locking, thereby producing an amplified seed light signal, and producing an optical signal using the amplified seed light signal and seed light injection locking, wherein the optical signal has about the same wavelength as the seed light signal. | 04-21-2011 |
Patent application number | Description | Published |
20090083485 | NONVOLATILE MEMORY WITH SELF RECOVERY - A nonvolatile memory array includes two or more devices, each device containing data that is scrambled using a different scrambling scheme. When the same data is provided and stored in both devices, different data patterns occur in each device, so that if one of the patterns causes data pattern induced errors, the original data can be recreated from another copy that does not share the same data pattern. | 03-26-2009 |
20090150596 | DEVICE IDENTIFIERS FOR NONVOLATILE MEMORY MODULES - A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system. | 06-11-2009 |
20090204824 | SYSTEM, METHOD AND MEMORY DEVICE PROVIDING DATA SCRAMBLING COMPATIBLE WITH ON-CHIP COPY OPERATION - Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key. | 08-13-2009 |
20090276570 | GUARANTEED MEMORY CARD PERFORMANCE TO END-OF-LIFE - In order to maintain a memory system's performance levels to its end-of-life, latency threshold level(s) are specified and associated with different memory system operating parameters. In one embodiment, the memory system monitors and gathers performance statistics in real time, and in accordance with specific memory transfer sizes. A current latency level can be dynamically calculated using the performance statistics and compared to previously established latency threshold levels. If the current latency level is greater than or equal to a specific latency threshold level, the memory system's configuration setting can be adjusted according to the operating parameters associated with the latency threshold level to offset the increased latency. | 11-05-2009 |
20110072328 | NONVOLATILE MEMORY CONTROLLER WITH SCALABLE PIPELINED ERROR CORRECTION - A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface. | 03-24-2011 |
20110161573 | DEVICE IDENTIFIERS FOR NONVOLATILE MEMORY MODULES - A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system. | 06-30-2011 |
20110271036 | PHASED NAND POWER-ON RESET - A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold. | 11-03-2011 |
20110320686 | FRDY PULL-UP RESISTOR ACTIVATION - A method and apparatus for reducing power consumption during an operation in a non-volatile storage device is disclosed. A non-volatile storage device controller that is in communication with a non-volatile memory in the non-volatile storage device receives a characteristic corresponding to a time duration required for the non-volatile memory to complete an operation. The controller disables a circuit that indicates when an operation by the non-volatile memory is complete. The controller then initiates the operation in the non-volatile memory, and maintains the circuit in a disabled state for a first predetermined time that is a portion of the time duration. The controller enables the circuit upon expiration of the first predetermined time and prior to the completion of the operation. The controller receives an indication of the completion of the operation via the circuit. | 12-29-2011 |
Patent application number | Description | Published |
20120017138 | Adaptive Flash Interface - A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased. | 01-19-2012 |
20120266048 | Dynamic Optimization of Back-End Memory System Interface - Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process. | 10-18-2012 |
Patent application number | Description | Published |
20090285853 | Nucleic Acids Encoding Respiratory Syncytial Virus Subgroup B strain 9320 - The complete polynucleotide sequence of the human respiratory syncytial virus subgroup B strain 9320 genome is provided. Proteins encoded by this polynucleotide sequence are also provided. Isolated or recombinant RSV (e.g., attenuated recombinant RSV), nucleic acids, and polypeptides, e.g., comprising mutations in the attachment protein G, are also provided, as are immunogenic compositions comprising such isolated or recombinant RSV, nucleic acids, and polypeptides. Related methods are also described. | 11-19-2009 |
20100330118 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, reassortant viruses, immunogenic compositions and vaccines comprising influenza hemagglutinin and neuraminidase variants and method using thereof are provided. | 12-30-2010 |
20120263744 | Compositions And Methods Involving Respiratory Syncytial Virus Subgroup B Strain 9320 - The complete polynucleotide sequence of the human respiratory syncytial virus subgroup B strain 9320 genome is provided. Proteins encoded by this polynucleotide sequence are also provided. Isolated or recombinant RSV (e.g., attenuated recombinant RSV), nucleic acids, and polypeptides, e.g., comprising mutations in the attachment protein G, are also provided, as are immunogenic compositions comprising such isolated or recombinant RSV, nucleic acids, and polypeptides. Related methods are also described. | 10-18-2012 |
20140079726 | INFLUENZA HEMAGGLUTININ AND NEURAMINIDASE VARIANTS - Polypeptides, polynucleotides, reassortant viruses, immunogenic compositions and vaccines comprising influenza hemagglutinin and neuraminidase variants and method using thereof are provided. | 03-20-2014 |