Patent application number | Description | Published |
20090047780 | Method for forming composite barrier layer - Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials. | 02-19-2009 |
20110006429 | BARRIER LAYERS FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer. | 01-13-2011 |
20110198757 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region. | 08-18-2011 |
20110291281 | PARTIAL AIR GAP FORMATION FOR PROVIDING INTERCONNECT ISOLATION IN INTEGRATED CIRCUITS - Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap. | 12-01-2011 |
20130026620 | SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME - The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body. | 01-31-2013 |
20130193593 | BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS - The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases. | 08-01-2013 |
20130233601 | SURFACE METAL WIRING STRUCTURE FOR AN IC SUBSTRATE - A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps. | 09-12-2013 |
20130252144 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler. | 09-26-2013 |
20140127898 | METHOD OF MAKING A SEMICONDUCTOR DEVICE INCLUDING BARRIER LAYERS FOR COPPER INTERCONNECT - A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer. | 05-08-2014 |
20140131864 | Connector Design for Packaging Integrated Circuits - A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar. | 05-15-2014 |
20140199812 | BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS - A method of forming a chip package includes providing a chip with a plurality of first copper post bumps having a first height of copper post. The method also includes providing a substrate with a plurality of second copper post bumps having a second height of copper post. The method further includes bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package. The first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1. | 07-17-2014 |