Patent application number | Description | Published |
20120292740 | HIGH VOLTAGE RESISTANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A HIGH VOLTAGE RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode. | 11-22-2012 |
20130207236 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra IN-type layer that reduces recombination of electrons and holes. | 08-15-2013 |
20140061721 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention. | 03-06-2014 |
20140175547 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-26-2014 |
20140175560 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region, a second doped region, and a gate structure. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The gate structure is formed on the first doped region and the second doped region. The gate structure comprises a first gate portion and a second gate portion, which are separated from each other by a gap. | 06-26-2014 |
20140191792 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND OPERATING METHOD FOR THE SAME - A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate. | 07-10-2014 |
20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 02-19-2015 |
20150179527 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-25-2015 |