Patent application number | Description | Published |
20130042080 | PREVENTION OF RACE CONDITIONS IN LIBRARY CODE THROUGH MEMORY PAGE-FAULT HANDLING MECHANISMS - Protection of shared data in a multi-core processing environment is disclosed. A page-fault handling mechanism is adapted to synchronize access to shared memory. An application of the present invention is for synchronizing access to potentially shared data, where the shared data is opaque in that it does not have a well-defined structure. | 02-14-2013 |
20130232315 | SCALABLE, CUSTOMIZABLE, AND LOAD-BALANCING PHYSICAL MEMORY MANAGEMENT SCHEME - A physical memory management scheme for handling page faults in a multi-core or many-core processor environment is disclosed. A plurality of memory allocators is provided. Each memory allocator may have a customizable allocation policy. A plurality of pagers is provided. Individual threads of execution are assigned a pager to handle page faults. A pager, in turn, is bound to a physical memory allocator. Load balancing may also be provided to distribute physical memory resources across allocators. Allocations may also be NUMA-aware. | 09-05-2013 |
20130283368 | SCALABLE AND SECURE APPLICATION RESOURCE MANAGEMENT AND ACCESS CONTROL FOR MULTICORE OPERATING SYSTEMS - An architecture for multi-core and many-core processor systems includes a set of resource managers having a hierarchy of at least one level. The resource managers act as trusted proxies for the operating system (OS) kernel to manage resources for applications. The application may include a trusted secure specification defining resource and access privileges of the associated application. | 10-24-2013 |
20140281363 | MULTI-THREADED MEMORY MANAGEMENT - Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device. | 09-18-2014 |
20140282589 | QUOTA-BASED ADAPTIVE RESOURCE BALANCING IN A SCALABLE HEAP ALLOCATOR FOR MULTITHREADED APPLICATIONS - One embodiment comprises a hierarchical heap allocator system. The system comprises a system-level allocator for monitoring run-time resource usage information for an application having multiple application threads. The system further comprises a process-level allocator for dynamically balancing resources between the application threads based on the run-time resource usage information. The system further comprises multiple thread-level allocators. Each thread-level allocator facilitates resource allocation and resource deallocation for a corresponding application thread. | 09-18-2014 |
20150032971 | System and Method for Predicting False Sharing - In one embodiment, a method for predicting false sharing includes running code on a plurality of cores and tracking potential false sharing in the code while running the code to produce tracked potential false sharing, where tracking the potential false sharing includes determining whether there is potential false sharing between a first cache line and a second cache line, and where the first cache line is adjacent to the second cache line. The method also includes reporting potential false sharing in accordance with the tracked potential false sharing to produce a false sharing report. | 01-29-2015 |
20150032973 | System and Method for Detecting False Sharing - In one embodiment, a method for detecting false sharing includes running code on a plurality of cores, where the code includes instrumentation and tracking cache invalidations in the code while running the code to produce tracked invalidations in accordance with the instrumentation, where tracking the cache invalidations includes tracking cache accesses to a plurality of cache lines by a plurality of tasks. The method also includes reporting false sharing in accordance with the tracked invalidations to produce a false sharing report. | 01-29-2015 |
20150234640 | System and Method for Isolating I/O Execution via Compiler and OS Support - Embodiments are provided for isolating Input/Output (I/O) execution by combining compiler and Operating System (OS) techniques. The embodiments include dedicating selected cores, in multicore or many-core processors, as I/O execution cores, and applying compiler-based analysis to classify I/O regions of program source codes so that the OS can schedule such regions onto the designated I/O cores. During the compilation of a program source code, each I/O operation region of the program source code is identified. During the execution of the compiled program source code, each I/O operation region is scheduled for execution on a preselected I/O core. The other regions of the compiled program source code are scheduled for execution on other cores. | 08-20-2015 |