Chauhan, TX
Maqbool Chauhan, Fort Worth, TX US
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20160073290 | FAULT ANALYTICS FRAMEWORK FOR QOS BASED SERVICES - A device may be configured to determine a current state of each of multiple operator network devices that provide a service via an operator network. The device may determine an allowable event at an operator network device based on the current state of the operator network device and model information that models behavior of the operator network device for the service. The device may monitor events at the operator network devices during a session. The device may detect that an allowable event for the operator network device does not occur during the session. The device may determine that a fault occurred at the operator network device during the session based on the allowable event not being detected at the operator network device. The device may provide fault information that indicates the fault occurred at the operator network device. | 03-10-2016 |
Rajnish S. Chauhan, Austin, TX US
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20120254602 | Methods, Systems, and Apparatuses for Managing a Hard Drive Security System - Methods, systems, and apparatuses for a self-encrypting drive (SED) management system configured to be loaded in a pre-boot region of an SED-based computer, the SED of the SED-based computer having a nominal space, which may be encrypted when the SED-based computer is shut down, and the pre-boot region. The SED management system comprises a pre-boot operating system (OS); at least one pre-boot library configured to support the pre-boot OS; and an unlocking software program configured to work with the pre-boot OS to transfer control directly to an operating system of the nominal space upon a successful authentication. Other embodiments are described and claimed. | 10-04-2012 |
20160063256 | Methods, Systems, and Apparatuses for Managing a Hard Drive Security System - A system for use with a computer is provided, the computer including a self-encrypting drive (SED), the SED including a nominal space and a pre-boot region, wherein the nominal space can be locked to prevent access to the nominal space. The system includes SED management software configured to be loaded in the pre-boot region of the SED. The SED management software includes a pre-boot operating system (OS) and an unlocking program. The unlocking program is configured (a) to execute within the pre-boot OS, and (b) upon successful authentication of a user, to unlock the nominal space of the SED. Other embodiments are described and claimed. | 03-03-2016 |
20160063259 | Methods, Systems, and Apparatuses for Managing a Hard Drive Security System - A system for use with a computer is provided, the computer including a self-encrypting drive (SED), the SED including a nominal space and a pre-boot region, wherein the nominal space can be locked to prevent access to the nominal space. The system includes SED management software configured to be loaded in the pre-boot region of the SED. The SED management software includes a pre-boot operating system (OS) and an unlocking program. The unlocking program is configured (a) to execute within the pre-boot OS, and (b) upon successful authentication of a user, to unlock the nominal space of the SED. Other embodiments are described and claimed. | 03-03-2016 |
Sadhana Chauhan, League City, TX US
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20090069248 | Substrate peptide sequences for plague plasminogen activator and uses thereof - The present invention is directed to peptide sequences that were identified from combinatorial libraries and could serve as substrates of plague plasminogen activator (Pla). Another aspect of the present invention is drawn to peptides derived from the substrates for Pla as a result of chemical modifications leading to specific inactivation of the proteolytic activity of Pla. Additionally, the present invention is directed to the use of the substrates identified herein in the detection of bacteria expressing omptin family of proteases which includes | 03-12-2009 |
Sadhana Chauhan, Leauge City, TX US
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20120045474 | Substrate peptide sequences for plague plasminogen activator and uses thereof - The present invention is directed to peptide sequences that were identified from combinatorial libraries and could serve as substrates of plague plasminogen activator (Pla). Another aspect of the present invention is drawn to peptides derived from the substrates for Pla as a result of chemical modifications leading to specific inactivation of the proteolytic activity of Pla. Additionally, the present invention is directed to the use of the substrates identified herein in the detection of bacteria expressing omptin family of proteases which includes | 02-23-2012 |
Satyendra Chauhan, Sugarland, TX US
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20100159643 | BONDING IC DIE TO TSV WAFERS - A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks. | 06-24-2010 |
Satyendra S. Chauhan, Sugar Land, TX US
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20090014898 | SOLDER CAP APPLICATION PROCESS ON COPPER BUMP USING SOLDER POWDER FILM - A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad. | 01-15-2009 |
Satyendra S. Chauhan, Dallas, TX US
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20090278244 | IC DEVICE HAVING LOW RESISTANCE TSV COMPRISING GROUND CONNECTION - A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame. | 11-12-2009 |
Satyendra S. Chauhan, Sugarland, TX US
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20090278245 | PACKAGED ELECTRONIC DEVICES WITH FACE-UP DIE HAVING TSV CONNECTION TO LEADS AND DIE PAD - A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad. | 11-12-2009 |
20120193814 | IC Device Having Low Resistance TSV Comprising Ground Connection - A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs. | 08-02-2012 |
20120202321 | IC Device Having Low Resistance TSV Comprising Ground Connection - A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV. | 08-09-2012 |
Satyendra Singh Chauhan, Sugar Land, TX US
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20080280394 | SYSTEMS AND METHODS FOR POST-CIRCUITIZATION ASSEMBLY - A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern. | 11-13-2008 |
20080283992 | Multi layer low cost cavity substrate fabrication for pop packages - In a method and system for fabricating a semiconductor device ( | 11-20-2008 |
20100062567 | Multi Layer Low Cost Cavity Substrate Fabrication for POP Packages - In a method and system for fabricating a semiconductor device ( | 03-11-2010 |
20100200961 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 08-12-2010 |
20100320575 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 12-23-2010 |
20110250720 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 10-13-2011 |
20130285260 | MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP - A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals. | 10-31-2013 |
Satyendra Singh Chauhan, Sugarland, TX US
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20090302438 | IC HAVING VOLTAGE REGULATED INTEGRATED FARADAY SHIELD - An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit. | 12-10-2009 |
20110183464 | DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS - A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article. | 07-28-2011 |
Siddharth Chauhan, Austin, TX US
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20090153818 | METHOD AND APPARATUS FOR EXTRACTING DOSE AND FOCUS FROM CRITICAL DIMENSION DATA - A method for monitoring a photolithography system includes defining a model of the photolithography system for modeling top and bottom critical dimension data associated with features formed by the photolithography system as a function of dose and focus. A library of model inversions is generated for different combinations of top and bottom critical dimension values. Each entry in the library specifies a dose value and a focus value associated with a particular combination of top and bottom critical dimension values. A top critical dimension measurement and a bottom critical dimension measurement of a feature formed by the photolithography system using a commanded dose parameter and a commanded focus parameter are received. The library is accessed using the top and bottom critical dimension measurements to generate values for a received dose parameter and the received focus parameter. The received dose and focus parameters are compared to the commanded dose and focus parameters to characterize the photolithography system. | 06-18-2009 |
20090157577 | METHOD AND APPARATUS FOR OPTIMIZING MODELS FOR EXTRACTING DOSE AND FOCUS FROM CRITICAL DIMENSION - A method includes defining a reference model of a system having a plurality of terms for modeling data associated with the system. A reference fit error metric is generated for the reference model. A set of evaluation models each having one term different than the reference model is generated. An evaluation fit error metric for each of the evaluation models is generated. The reference model is replaced with a selected evaluation model responsive to the selected evaluation model having an evaluation fit error metric less than the reference fit error metric. The model evaluation is repeated until no evaluation model has an evaluation fit error metric less than the reference fit error metric. The reference model is trained using the data associated with the system, and the trained reference model is employed to determine at least one characteristic of the system. | 06-18-2009 |