Chao-Yang
Chao-Yang Chen, New Taipei City 234 TW
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20130094915 | POSITIONING SLEEVE FOR ELECTRICAL DRILL DUST COLLECTOR AND ELECTRICAL DRILL DUST COLLECTOR USING THE POSITIONING SLEEVE - The invention relates to a positioning sleeve for an electrical drill dust collector and an electrical drill dust collector using the positioning sleeve. The positioning sleeve comprises: a sleeve portion coupled with a flange at a front edge of an electrical drill and a support body forward extended from the sleeve portion, surrounding and isolating a rotated portion of the electrical drill to enhance the drill operating safety. The electrical drill dust collector using the aforesaid positioning sleeve comprises: a fixing base fixing on the support body, a telescoping sleeve having a ring body at an front end thereof, a dust collection section at a front end section thereof and a bellows section at a tail end section thereof, and an elastic member having a positioning end connected to the fixing base and a free end thereof connected to the ring body to improve the dustproof effect. | 04-18-2013 |
Chao-Yang Chen, Taipei City TW
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20130251964 | Composite Board - A composite board with landscaping and decorative functions is disclosed. The composite board has a first decoration layer, a first interlayer, and a first protection layer. The first interlayer is located under the first decoration layer. The first decoration layer is located under the first protection layer. The first interlayer is made of 3D fiberglass impregnated with a resin. | 09-26-2013 |
Chao-Yang Hsiao, Hsi Chih City TW
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20100159751 | USB CONNECTOR AND CONTACT ARRAY THEREOF - Disclosed herein is a contact array of a universal serial bus (USB) connector including a first signal differential pair, a second signal differential pair and a third signal differential pair, wherein the second signal differential pair is disposed between the first and third signal differential pairs, and at least one power contact or ground contact is disposed between the first and second signal differential pairs, or between the second and third signal differential pairs. | 06-24-2010 |
Chao-Yang Hsu, Taipei TW
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20100002447 | LIGHT-GUIDING ELEMENT, LIGHT-EMITTING MODULE, AND ELECTRONIC DEVICE - A light-guiding element cooperates with a light source and includes a light-guiding frame and a scattering material. The light-guiding frame has a light incident surface, a light output surface, and an inclined surface. Light emitted by the light source enters into the light-guiding frame through the light incident surface, and the light is reflected by the inclined surface to be outputted through the light output surface. The scattering material is disposed at the inclined surface. A light-emitting module having the light-guiding element and an electronic device are also disclosed. | 01-07-2010 |
20130258606 | DISPLAY DEVICE WITH REPLACEABLE HOUSING - A display device with a replaceable housing, applicable to an electronic product using a flip form, includes: a display panel module, a positioning plate, and an outer cover. The display panel module has a display portion on one side thereof. The positioning plate has a frame piece and a metal plate. The frame piece is disposed at the periphery of the display panel module. The metal plate is fixed at the frame piece to cover the other side of the display panel module. The outer cover is detachably joined with the positioning plate and covers the positioning plate. | 10-03-2013 |
20140268962 | HYBRID DC/AC INVERTER - A hybrid DC/AC inverter for converting DC power to AC power feed to a grid voltage system has an input circuit, a half/full bridge switchable circuit and an output circuit. The input circuit has two input terminals for connecting to a DC source and outputs the DC power. The half/full bridge switchable circuit can be operated in a buck mode based on amplitudes of the DC power and the grid voltage. The output circuit is for connecting to the grid voltage system. According to comparison results between of the DC power and the grid voltage, the half/full bridge switchable circuit is selectively operated in the buck mode to reduce switching loss and power consumption. | 09-18-2014 |
Chao-Yang Huang, Xizhi City TW
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20090162378 | ANTI-HUMAN CYTOMEGALOVIUS ANTIBODIES - The present invention features a human antibody that specifically binds to human cytomegalovirus (HCMV), its encoding nucleic acid(s), and use of the antibody/nucleic acid(s) in treating HCMV infection. | 06-25-2009 |
Chao-Yang Huang, Taichung City TW
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20110303540 | PHOTO-CATALYST OZONE DETECTOR - A photo-catalyst ozone detector includes a base. A positive electrode and a negative electrode are respectively disposed on the base. A photo-catalyst coating is disposed on the base for connecting the positive electrode and the negative electrode, and reacting with the ozone to detect ozone consistency, wherein the photo-catalyst coating contains titanium dioxide. | 12-15-2011 |
Chao-Yang Huang, Yuanlin Township TW
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20150183182 | MULTI-FUNCTIONAL CUSHION BODY - A multi-functional cushion body has a microporous layer, pores of which are filled with cooling objects or heating objects offering a feeling of coolness or warmth in contact with the human skin. The multi-functional cushion body is either of a shoe cushion, footing cushion, back cushion, seat cushion, bra cushion, cupboard deodorizer cushion or antibacterial cushion. The cooling or heating objects in the multi-functional cushion body evaporate slowly, thus extending the service life. The multi-functional cushion body can be fabricated easily due to simple structure. | 07-02-2015 |
Chao-Yang Huang, New Taipei City TW
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20140186352 | ANTI-GRANULYSIN ANTIBODIES AND METHODS OF USE THEREOF - An anti-granulysin antibody, or an scFv or Fab fragment thereof, capable of binding to an epitope region from R64 to R113 of granulysin and capable of neutralizing an activity of granulysin. The antibody may contain a sequence selected from the sequences of SEQ ID NO:82 to SEQ ID NO:195, or the antibody may contain a sequence selected from the sequences of SEQ ID NO:39 to SEQ ID NO:76. The antibody may be a monoclonal antibody. A method for treating or preventing an unwanted immune response disorder includes administering to a subject in need thereof an effective amount of an anti-granulysin antibody capable of neutralizing the activity of granulysin. The unwanted immune response disorder may be SJS, TEN, or GVHD. | 07-03-2014 |
20140314741 | Human Antibody against Interleukin-20 and Treatment for Inflammatory Diseases - FLB5M5 is a humanized monoclonal antibody with three mutated amino acids in the CDRs relative to its parental mouse anti-IL-20 monoclonal antibody 7E and five mutated amino acids of the light-chain framework region relative to the amino acids of the light-chain framework region of human Vκ2. FLB5M5 not only retains binding specificity toward IL-20 but also has a better binding affinity than 7E for IL-20. FLB5M5 is also less immunogenic than 7E to the human host in clinical application. A mutation in the light chain CDR to tyrosine increases binding affinity to IL-20. A method for treating rheumatoid arthritis using FLB5M5 is also disclosed. | 10-23-2014 |
Chao-Yang Kuo, Zhubei City TW
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20150338994 | TOUCH CONTROL DEVICE AND METHOD, AND METHOD FOR FORMING TOUCH CONTROL DEVICE - A touch control device capable of preventing false positives is provided. The touch control device includes: a conductive plate, electrically connected to a predetermined potential; a sensing region, located above the conductive plate, including a plurality of capacitive sensing units; and a conductive ring, located above the conductive plate, disposed at a periphery of the sensing region. When a touch scanning signal is provided to one on-duty capacitive touch sensing unit of the capacitive touch sensing units, the conductive ring synchronously receives a control signal associated with the touch scanning signal. | 11-26-2015 |
Chao-Yang Lee, Taipei City TW
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20140155633 | Composition for Stabilizing Ascorbic Acid Derivatives and the Application Thereof - This invention discloses a composition for stabilizing ascorbic acid derivative and the application thereof. The mentioned composition comprises ascorbic acid derivative, buffer, phosphonic acid derivative and at least one alcohol. The yellowish and degradation of ascorbic acid derivative can be efficiently decreased by the mentioned composition. Moreover, the mentioned composition can be used in topical composition, such as toner, serum, lotion, cream. | 06-05-2014 |
Chao-Yang Liu, Ta-Li City TW
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20090272645 | Corrosion resistant gas diffusion layer with a micro protective layer for electrochemical cells - A gas diffusion layer with a micro protective layer is utilized in the electrochemical cells. The cell mainly includes end plates, current collectors, flow field plates, gas diffusion layers, catalyst layers, a proton exchange membrane and a circuit unit. When the cell functions as a fuel cell, hydrogen reacts with oxygen to generate electricity and water. Reversely, when the cell functions as a water electrolysis cell, water was decomposed electrolytically to produce hydrogen and oxygen gases. In this manner, the present invention particularly has the gas diffusion layer to be coated with a micro protective layer so as to prevent the gas diffusion layer from being corroded by active oxygen species generated within the oxygen electrode under the catalysis during water electrolysis operation. | 11-05-2009 |
Chao-Yang Song, Dongguan CN
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20140368302 | RELAY CONTACT SYSTEM - A relay contact system includes a first conductive plate, a first resilient plate, a second conductive plate and a second resilient plate. One end of the first conductive plate is a free end, and another opposing end is a connecting end. One end of the first resilient plate is a free end provided with a first contact, and another opposing end is a connecting end. The connecting ends of the first conductive plate and the first resilient plate are connected together. The free ends of the first conductive plate and the first resilient plate are arranged in the same direction and form a first zigzag configuration. The second conductive plate and the second resilient plate having a second contact on its free end and form a second zigzag configuration. The first and second zigzag configurations are connected or disconnected through the first and second contacts. | 12-18-2014 |
Chao-Yang Sun, Su Zhou City CN
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20120327853 | Transmission Method of Femtocell - A transmission method of a femtocell includes the following steps. The femtocell receives and temporarily stores multiple real-time transport protocol (RTP) packets from a UE in a buffer. When the RTP packets are temporarily stored for a time period, the femtocell samples the buffer at a sampling rate to generate multiple CS data packets. The CS data packets include a current CS data packet. When there exists no previous CS data packet received from the UE, the femtocell calculates a timestamp of the current CS data packet according to a current timestamp. When there exists the previous CS data packet, the femtocell calculates the timestamp of the current CS data packet according to the timestamp and a connection frame number (CFN) of the previous CS data packet and a CFN of the current CS data packet. | 12-27-2012 |
Chao-Yang Tsai, New Taipei City TW
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20140266350 | SIGNAL GENERATING CIRCUIT AND METHOD THEREOF - A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal. | 09-18-2014 |
Chao-Yang Tsai, Kaohsiung City TW
Chao-Yang Wang, Pennsylvania, PA US
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20120025773 | METHOD OF CHARGING BATTERY AND BATTERY CHARGING CONTROL SYSTEM - A controller in a charging control system controls a charger to heat a battery at a low temperature by pulse charging and discharging up to a desired temperature and then moves to a normal charging mode. The controller calculates an ion concentration of an active material at electrode portions of the battery on the basis of the temperature data and the electric current data obtained, switch the pulse charging and discharging between a charging mode and a discharging mode on the basis of a pulse width when the ion concentration reaches a threshold. | 02-02-2012 |
Chao-Yang Yeh, Luzhou City TW
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20120273782 | INTERPOSERS OF 3-DIMENSIONAL INTEGRATED CIRCUIT PACKAGE SYSTEMS AND METHODS OF DESIGNING THE SAME - An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer. | 11-01-2012 |
20130007692 | TOOL AND METHOD FOR MODELING INTERPOSER RC COUPLINGS - A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium. | 01-03-2013 |
20130147505 | TEST PROBING STRUCTURE - A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps. | 06-13-2013 |
20130167095 | STACKED DIE INTERCONNECT VALIDATION - A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns. | 06-27-2013 |
20140183692 | TECHNIQUES FOR FAST RESONANCE CONVERGENCE - Some methods provide an electronic design file, which includes an integrated circuit (IC) component that is operably coupled to a package component. The IC component and package component collectively form a resistor inductor capacitor (RLC) resonant circuit. The method also provides a damping component in the electronic design file. This damping component is configured to reduce a pre-resonant time during which energy exchanged in the RLC resonant circuit approaches a steady-state, and thereby speeds simulation time. | 07-03-2014 |
20140282305 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 09-18-2014 |
20150154343 | SYSTEMS AND METHODS FOR DETERMINING EFFECTIVE CAPACITANCE TO FACILITATE A TIMING ANALYSIS - A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values. | 06-04-2015 |
20150213182 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 07-30-2015 |
20150234979 | SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS - A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns. | 08-20-2015 |