Patent application number | Description | Published |
20080288807 | SYSTEM, METHOD, AND COMPUTER PROGRAM FOR PRESENTING AND UTILIZING FOOTPRINT DATA AS A DIAGNOSTIC TOOL - A data processing system for storing and identifying footprint data in a data processing system enabling automated collection, identification and formatting recovery of footprint data executing on a mainline routine. A footprint area is allocated onto a failure recovery routine stack for use by the mainline routine for storing footprint data. The mainline routine stores footprint data within the first footprint area. The data processing system can then receive a request from a diagnostic tool, where the request includes at least one search parameter. The data processing system can output any footprint data to a diagnostic tool corresponding to the search parameters in the request. | 11-20-2008 |
20080294864 | MEMORY CLASS BASED HEAP PARTITIONING - The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester. | 11-27-2008 |
20080295081 | FRAMEWORK FOR CONDITIONALLY EXECUTING CODE IN AN APPLICATION USING CONDITIONS IN THE FRAMEWORK AND IN THE APPLICATION - A computer implemented method, apparatus, and computer usable program code for returning a return code to an error hook in an application using a framework. An identifier and a pass-through are received from the error hook. The error hook is software code in the application. The pass-through is a set of parameters. If the identifier has an active status, a set of framework conditions is retrieved using the identifier. If the set of framework conditions is met, an inject callback is retrieved using the error identifier. The inject callback is called with the error identifier and the pass-through. An inject callback return code is received. If the inject callback return code is an execute return code, the execute return code is returned to the error hook. | 11-27-2008 |
20080307182 | EFFICIENT AND FLEXIBLE MEMORY COPY OPERATION - A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline. | 12-11-2008 |
20090138664 | CACHE INJECTION USING SEMI-SYNCHRONOUS MEMORY COPY OPERATION - A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory. | 05-28-2009 |
20090144737 | DYNAMIC SWITCHING OF MULTITHREADED PROCESSOR BETWEEN SINGLE THREADED AND SIMULTANEOUS MULTITHREADED MODES - An apparatus and program product utilize a multithreaded processor having at least one hardware thread among a plurality of hardware threads that is capable of being selectively activated and deactivated responsive to a control circuit. The control circuit additionally provides the capability of controlling how an inactive thread can be activated after the thread has been deactivated, e.g., by enabling or disabling reactivation in response to an interrupt. | 06-04-2009 |
20090182968 | VALIDITY OF ADDRESS RANGES USED IN SEMI-SYNCHRONOUS MEMORY COPY OPERATIONS - A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed. | 07-16-2009 |
20120191908 | STORAGE WRITES IN A MIRRORED VIRTUAL MACHINE SYSTEM - Performing storage writes in a mirrored virtual machine system by receiving a state of a primary virtual machine during execution of an application, wherein the primary virtual machine runs on a first physical machine and a secondary virtual machine runs on a second physical machine, wherein the state is captured by checkpointing, and the primary virtual machine is configured to write data to a first block and concurrently write the data to a write buffer on the secondary virtual machine. The method also includes storing a copy of data within a second block to a rollback buffer for the secondary virtual machine, in response to identifying a checkpoint in the application, merging the rollback buffer with the write buffer, in response to detecting a failover, writing a copy of the rollback buffer to the disk storage, and continuing execution on the secondary virtual machine from the last checkpoint. | 07-26-2012 |
20120216078 | FRAMEWORK FOR CONDITIONALLY EXECUTING CODE IN AN APPLICATION USING CONDITIONS IN THE FRAMEWORK AND IN THE APPLICATION - A computer implemented method, apparatus, and computer usable program code for returning a return code to an error hook in an application using a framework. An identifier and a pass-through are received from the error hook. The error hook is software code in the application. The pass-through is a set of parameters. If the identifier has an active status, a set of framework conditions is retrieved using the identifier. If the set of framework conditions is met, an inject callback is retrieved using the error identifier. The inject callback is called with the error identifier and the pass-through. An inject callback return code is received. If the inject callback return code is an execute return code, the execute return code is returned to the error hook. | 08-23-2012 |
20130151577 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 06-13-2013 |
20130151578 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 06-13-2013 |
20130152098 | TASK PRIORITY BOOST MANAGEMENT - According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread. | 06-13-2013 |
20140143458 | Offloading Input/Output (I/O) Completion Operations - A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure. | 05-22-2014 |
20140143465 | Offloading Input/Output (I/O) Completion Operations - A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure. | 05-22-2014 |
20150058840 | Sharing Resources Allocated to an Entitled Virtual Machine - A mechanism is provided for sharing resources allocated to an entitled virtual machine (VM). A blocked domain is created around the entitled VM and one or more processors allocated to the entitled VM. A first dispatching algorithm is implemented that prevents the dispatching of processes from other operating systems within other VMs to the one or more processors allocated to the entitled VM. Responsive to utilization of the one or more processors allocated to the entitled VM falling below a predetermined threshold, a second dispatching algorithm is implemented that allows dispatching of processes from the other operating systems within the other VMs to the one or more processors allocated to the entitled VM. | 02-26-2015 |
20150058842 | Sharing Resources Allocated to an Entitled Virtual Machine - A mechanism is provided for sharing resources allocated to an entitled virtual machine (VM). A blocked domain is created around the entitled VM and one or more processors allocated to the entitled VM. A first dispatching algorithm is implemented that prevents the dispatching of processes from other operating systems within other VMs to the one or more processors allocated to the entitled VM. Responsive to utilization of the one or more processors allocated to the entitled VM falling below a predetermined threshold, a second dispatching algorithm is implemented that allows dispatching of processes from the other operating systems within the other VMs to the one or more processors allocated to the entitled VM. | 02-26-2015 |
20150074162 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 03-12-2015 |