Patent application number | Description | Published |
20080248771 | CALIBRATION TECHNIQUES FOR FREQUENCY SYNTHESIZERS - In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device. | 10-09-2008 |
20080284508 | OUTPUT CIRCUITS WITH CLASS D AMPLIFIER - Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal. | 11-20-2008 |
20090161588 | SYSTEMS AND METHODS FOR CONTROLLING THE VOLTAGE OF SIGNALS USED TO CONTROL POWER AMPLIFIERS - A method for controlling the voltage of signals used to control power amplifiers is described. A first multiplexer and a second multiplexer are set to an enabling signal. The first multiplexer is on a first integrated circuit and the second multiplexer is on a second integrated circuit. A command is written to the first multiplexer to set the first multiplexer to one of a plurality of control signals used to control a power amplifier. A command is written to the second multiplexer to select one of the plurality of control signals that maps to the first multiplexer. The second integrated circuit is connected to a power supply. | 06-25-2009 |
20100064074 | SINGLE WIRE BUS INTERFACE - Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices. | 03-11-2010 |
20110105070 | Direct conversion receiver architecture - A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. | 05-05-2011 |
20110285463 | OUTPUT CIRCUITS WITH CLASS D AMPLIFIER - Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal. | 11-24-2011 |
20110285472 | OUTPUT CIRCUITS WITH CLASS D AMPLIFIER - Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal. | 11-24-2011 |
20140210482 | METHOD AND APPARATUS FOR REDUCING COMMON MODE VARIATIONS IN A VOLTAGE SENSING COMPONENT - A method and apparatus that reduce common mode variations experienced by a voltage sensing component. A measurement component such as a BATFET or an external sensing resistor, receives, at its source, a voltage from the top of a battery having a voltage VPH_PWR. A voltage sensing component, such as an ADC, is powered by the voltage from the battery. A power referenced component, such as a power referenced LDO, tracks the voltage from the battery and outputs the tracked voltage minus a predetermined voltage amount to a negative side of the voltage sensing component. | 07-31-2014 |