Patent application number | Description | Published |
20080301509 | METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS BY EMPLOYING TEST VECTOR PATTERNS THAT SATISFY PASSBAND REQUIREMENTS IMPOSED BY COMMUNICATION CHANNELS - Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel. | 12-04-2008 |
20090115443 | SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUIT MODULES COMPRISING A PLURALITY OF INTEGRATED CIRCUIT DEVICES - Embodiments of a system and method for testing an integrated circuit module comprising multiple integrated circuit devices, such as a memory module comprising multiple memory devices for example, is disclosed. Embodiments of the method may be employed to test an integrated circuit device of the integrated circuit module that provides a data strobe signal associated with at least one data signal provided by the same integrated circuit device. A determination of a test outcome for the integrated circuit module may be made after identifying data valid windows for each integrated circuit device, without having to both identify a common sampling window defined by an intersection of the identified data valid windows and verify that such common sampling window meets specification requirements, as may be performed by conventional testers. | 05-07-2009 |
20090306925 | SYSTEMS AND METHODS FOR TESTING INTEGRATED CIRCUIT DEVICES - Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a controller coupled to at least one coupling between a processor and a first reference integrated circuit device of an application system, wherein the first controller is configured to: tap the first test data transmitted via the at least one coupling; transmit second test data to a second reference integrated circuit device, wherein the second test data comprises at least a portion of the first test data; receive reference response data from the second reference integrated circuit device in response to the second test data transmitted thereto; transmit the second test data to at least one integrated circuit device under test; and transmit the reference response data to at least one comparator coupled to the at least one integrated circuit device under test. | 12-10-2009 |
20110179324 | TESTING APPARATUS AND METHOD FOR ANALYZING A MEMORY MODULE OPERATING WITHIN AN APPLICATION SYSTEM - A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis. | 07-21-2011 |
20120047411 | DETERMINING DATA VALID WINDOWS IN A SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE - Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable. In at least one embodiment, the method comprises: for each individual data bit region of one or more data bit regions of a second data signal, sampling the second data signal at a plurality of points of the individual data bit region to produce a plurality of sampled values for the second data signal; for each sampled value of the plurality of sampled values, determining whether the sampled value matches an expected bit pattern value corresponding to the sampled value; determining one or more characteristics of the data valid window that defines conditions under which a valid sample can be expected to be taken; and outputting a test outcome based on one or more characteristics of the data valid window. In some embodiments, the second data signal may be sampled at the plurality of points of the individual data bit region concurrently. In some embodiments, the determination of whether each sampled value of the plurality of sampled values matches the expected bit pattern value may be performed concurrently for all of the plurality of sampled values. | 02-23-2012 |
20130058178 | SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUITS BY DETERMINING THE SOLID TIMING WINDOW - Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, the solid timing window used to determine a key timing index. The key timing index provides an indication of the quality of an integrated circuit over a range of operating conditions. In at least one embodiment a method is provided, the method comprising generating a plurality of combinations of operating parameters, for each of the plurality of combinations of operating parameters setting the respective combination of operating parameters, operating the integrated circuit under the set respective combination of operating parameters, and determining a data valid window for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of combinations of operating parameters, where the solid operating timing window is the logical intersection of the determined data valid windows. | 03-07-2013 |
20140068360 | SYSTEMS AND METHODS FOR TESTING MEMORY - Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system. | 03-06-2014 |
20140211580 | SYSTEMS AND METHODS FOR TESTING AND ASSEMBLING MEMORY MODULES - Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor. | 07-31-2014 |