Patent application number | Description | Published |
20100058358 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 03-04-2010 |
20110153955 | SOFTWARE ASSISTED TRANSLATION LOOKASIDE BUFFER SEARCH MECHANISM - A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified translation lookaside buffer is then searched according to the first order code for a hashed page entry. If the hashed page entry is not found when searching a unified translation lookaside buffer according to the first order code, a second order code is identified within a second entry of the search priority configuration register. The unified translation lookaside buffer is then searched according to the second order code for the hashed page entry. | 06-23-2011 |
20110296148 | Transactional Memory System Supporting Unbroken Suspended Execution - Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued. | 12-01-2011 |
20130007408 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 01-03-2013 |
20150120985 | MECHANISMS FOR ELIMINATING A RACE CONDITION BETWEEN A HYPERVISOR-PERFORMED EMULATION PROCESS REQUIRING A TRANSLATION OPERATION AND A CONCURRENT TRANSLATION TABLE ENTRY INVALIDATION - Disclosed are computers and methods employing a mechanism for eliminating a race condition between a hypervisor-performed emulation process and a concurrent translation table entry invalidation. Specifically, on a host machine, a hypervisor controls any guest operating systems. In doing so, the hypervisor emulates an instruction by performing a translation operation to acquire a physical address from a virtual address and, if applicable, further from an effective address using translation table(s) (e.g., page tables and, if applicable, segment tables); accesses the physical address; and completes the instruction. During emulation, flagged address table(s) are used to eliminate the race condition. For example, upon receiving an invalidate translation instruction associated with a virtual address, a determination is made as to whether or not the virtual address appears in a flagged virtual address table and, if so, additional action is taken to prevent an error in the translation. | 04-30-2015 |
20150301939 | MANAGING TRANSLATIONS ACROSS MULTIPLE CONTEXTS USING A TLB WITH ENTRIES DIRECTED TO MULTIPLE PRIVILEGE LEVELS AND TO MULTIPLE TYPES OF ADDRESS SPACES - For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space. | 10-22-2015 |
20150301950 | MANAGING TRANSLATION OF A SAME ADDRESS ACROSS MULTIPLE CONTEXTS USING A SAME ENTRY IN A TRANSLATION LOOKASIDE BUFFER - In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value. | 10-22-2015 |
20150301951 | MANAGING TRANSLATIONS ACROSS MULTIPLE CONTEXTS USING A TLB WITH ENTRIES DIRECTED TO MULTIPLE PRIVILEGE LEVELS AND TO MULTIPLE TYPES OF ADDRESS SPACES - For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space. | 10-22-2015 |
20150301953 | MANAGING TRANSLATION OF A SAME ADDRESS ACROSS MULTIPLE CONTEXTS USING A SAME ENTRY IN A TRANSLATION LOOKASIDE BUFFER - In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value. | 10-22-2015 |