Bchir
Omar Bchir, San Marcos, CA US
Patent application number | Description | Published |
---|---|---|
20130299226 | MECHANICAL ADHESION OF COPPER METALLIZATION TO DIELECTRIC WITH PARTIALLY CURED EPOXY FILLERS - In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed. | 11-14-2013 |
Omar James Bchir, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20140264946 | PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT - To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window. | 09-18-2014 |
Omar James Bchir, San Marcos, CA US
Patent application number | Description | Published |
---|---|---|
20140322868 | BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE - Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized. | 10-30-2014 |
20150061143 | ULTRA FINE PITCH AND SPACING INTERCONNECTS FOR SUBSTRATE - Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer. | 03-05-2015 |