Patent application number | Description | Published |
20090170255 | INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS - A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure. | 07-02-2009 |
20100213974 | Method and apparatus for camouflaging a printed circuit board - A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells. | 08-26-2010 |
20100218158 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT - A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. | 08-26-2010 |
20100301903 | BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY - A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt. | 12-02-2010 |
20120139582 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT WITH MICRO CIRCUITS AND POST PROCESSING - A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit. | 06-07-2012 |
20130191803 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT - A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logic cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. | 07-25-2013 |