Patent application number | Description | Published |
20080265982 | METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 10-30-2008 |
20090153228 | STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 06-18-2009 |
20110107291 | DESIGN SYSTEM AND METHOD THAT, DURING TIMING ANALYSIS, COMPENSATES FOR REGIONAL TIMING VARIATIONS - Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths. | 05-05-2011 |
20110173583 | METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF - A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit. | 07-14-2011 |
20130185684 | INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM - Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit. | 07-18-2013 |
20130332895 | METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF - A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit. | 12-12-2013 |