Patent application number | Description | Published |
20110228367 | GIMBALED SCANNING MICRO-MIRROR APPARATUS - Provided is a Micro-Electro-Mechanical Systems (MEMS) device for actuating a gimbaled element, the device including a symmetric electromagnetic actuator for actuating one degree of freedom (DOF) and a symmetric electrostatic actuator for actuating the second degree of freedom. | 09-22-2011 |
20120235779 | MICRO COIL APPARATUS AND MANUFACTURING METHODS THEREFOR - A method for manufacturing a conductive coil, the method comprising using a semiconductor fabrication process (e.g. TSV) to manufacture a coil, typically a planar spiral conductive coil. | 09-20-2012 |
20140320944 | GIMBALED SCANNING MICRO-MIRROR APPARATUS - A Micro-Electro-Mechanical Systems (MEMS) device for actuating a gimbaled element, the device comprising a symmetric electromagnetic actuator for actuating one degree of freedom (DOF) and a symmetric electrostatic actuator for actuating the second degree of freedom. | 10-30-2014 |
20140355095 | MULTI-PURPOSE OPTICAL CAP AND APPARATUS AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for protecting an optical MEMS device, including providing an optical MEMS device defining a field of view and including layers which define a main plane; and forming a protective element, constructed and operative for at least partly covering the optical MEMS device, from an optical structural material and wherein the protective element includes a planar portion tilted with respect to said main plane via which a majority of light energy directed toward said main plane must pass. | 12-04-2014 |
Patent application number | Description | Published |
20080301341 | Management Of Internal Operations By A Storage Device - A method enables a storage device to autonomously (i.e., without intervention of a host device) determines whether an integral sequence of commands, which is related to one or more storage commands issued by the host device, is in a certain state (i.e., it is “active” or “inactive”) or is transitioning from “active” state to “inactive” state, or from “inactive” state to “active” state. Depending on the determined state or transition, the storage device determines whether to refrain from executing Extra-Sequence (“ESQ”) operations and permit executing Intra-Sequence (“ISQ”) operations, or vice versa. | 12-04-2008 |
20100154062 | Virus Scanning Executed Within a Storage Device to Reduce Demand on Host Resources - Protection against computer viruses is provided by a storage device having a memory, a controller, and a content scanning module used for scanning files for viruses. Infected files are indicated to a virus handling module that resides external to the storage device. The virus handling module may alter access to the infected files and/or indicate their presence to other system components. Such virus scanning mechanism can be built within the controller of the storage device. The protection against computer viruses may be provided by a method that includes transferring file data from the memory to the controller, reconstructing the files from the file data, activating the controller to check the reconstructed files for viruses, and indicating the infected files to the virus handling module. By using the controller within the storage device to scan for viruses, the burden on the host can be greatly reduced. | 06-17-2010 |
20100299456 | MANAGEMENT OF INTERNAL OPERATIONS BY A STORAGE DEVICE - A method of handling internal operations of a storage device includes in response to information derived from one or more commands received from a host device when the storage device is coupled to the host device, determining whether a sequence of commands is in one of an active state, and a first transition state, where in the first transition state the sequence of commands is transitioning from an inactive state to the active state. The method includes, while the sequence of commands is in the active state or in the first transition state, refraining from executing any operation of a first set of internal memory management operations, each of the first set of internal memory management operations being an extra-sequence operation. | 11-25-2010 |
Patent application number | Description | Published |
20140149625 | METHOD AND APPARATUS FOR DMA TRANSFER WITH SYNCHRONIZATION OPTIMIZATION - A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data. | 05-29-2014 |
20140223073 | MANAGEMENT OF RANDOM CACHE READ OPERATIONS - A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence. | 08-07-2014 |
20140245040 | Systems and Methods for Managing Data in a System for Hibernation States - The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level. | 08-28-2014 |
20140344536 | STORAGE SYSTEMS THAT CREATE SNAPSHOT QUEUES - A storage system may include a queue included in a memory and a controller configured to store commands received from a host in the queue. The queue may have a linked-list configuration. In response to a triggering event, the controller may take a snapshot of the queue, creating a snapshot queue. The snapshot queue may have a linear configuration. Subsequent analysis or parsing of queued information may be performed on the linear snapshot queue instead of the linked-list queue. Modifications to the linear snapshot queue may be corresponding made to the linked-list queue. | 11-20-2014 |
20140351456 | COMMAND AND DATA SELECTION IN STORAGE CONTROLLER SYSTEMS - A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached. | 11-27-2014 |
20150186068 | COMMAND QUEUING USING LINKED LIST QUEUES - A method, apparatus, and system may be provided for queuing storage commands. A command buffer may store storage commands for multiple command queues. Linked list controllers may control linked lists, where each one of the linked lists identifies the storage commands that are in a corresponding one of the command queues. The linked list storage memory may store next command pointers for the storage commands. A linked list element in any of the linked lists may include one of the storage commands stored in the command buffer and a corresponding one of the next command pointers stored in the linked list storage memory. | 07-02-2015 |
20160041774 | COMMAND AND DATA SELECTION IN STORAGE CONTROLLER SYSTEMS - A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached. | 02-11-2016 |