Bahukhandi
Ashirwad Bahukhandi, San Jose, CA US
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20120287316 | RAMP AND SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERSION METHODS, SYSTEMS AND APPARATUS - Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps. | 11-15-2012 |
20130134295 | IMAGING SYSTEMS WITH SELECTABLE COLUMN POWER CONTROL - Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry. The column readout circuitry on each column line may include signal processing circuitry and a latch circuit. The latch circuit on each column line may be used to selectively enable and disable the signal processing circuitry on that column line. Each latch circuit may be coupled to first and second signal lines for globally enabling and disabling the signal processing circuitry on all of the column lines. Each latch circuit may be coupled to column decoder circuitry. The column decoder circuitry may provide a column-select signal to latch circuits on a chosen subset of column lines that enables the signal processing circuitry on those column lines by setting those latch circuits. | 05-30-2013 |
Ashirwad Bahukhandi, Milpitas, CA US
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20130070135 | COLUMN PARALLEL READOUT IMAGE SENSORS WITH SHARED COLUMN ANALOG-TO-DIGITAL CONVERTER CIRCUITRY - Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array. | 03-21-2013 |
Ashirwad Bahukhandi, Santa Clara, CA US
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20130308028 | OFFSET INJECTION IN AN ANALOG-TO-DIGITAL CONVERTER - An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal. | 11-21-2013 |
Ashirwad Bahukhandi, Cupertino, CA US
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20150350575 | PIXEL BINNING IN AN IMAGE SENSOR - Pixel binning is performed by summing charge from some pixels positioned diagonally in a pixel array. Pixel signals output from pixels positioned diagonally in the pixel array may be combined on the output lines. A signal representing summed charge produces a binned 2×1 cluster. A signal representing combined voltage signals produces a binned 2×1 cluster. A signal representing summed charge and a signal representing combined pixel signals can be combined digitally to produce a binned 2×2 pixel. Orthogonal binning may be performed on other pixels in the pixel array by summing charge on respective common sense regions and then then combining the voltage signals that represent the summed charge on respective output lines. | 12-03-2015 |