Patent application number | Description | Published |
20080235492 | APPARATUS FOR COMPRESSING INSTRUCTION WORD FOR PARALLEL PROCESSING VLIW COMPUTER AND METHOD FOR THE SAME - An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each of instruction word groups to be executed in a VLIW computer; an instruction compression unit sequentially deleting the NOP instruction word which corresponds to the index code with respect to each of instruction word groups; and an instruction word conversion unit converting the effective instruction words to include the index code, the effective instruction words corresponding to the NOP instruction words. | 09-25-2008 |
20080235657 | LOOP COALESCING METHOD AND LOOP COALESCING DEVICE - A loop coalescing method and a loop coalescing device are disclosed. The loop coalescing method comprises removing an inner-most loop from among nested loops, so that an outer operation provided outside of the inner-most loop is performed when a condition of a conditional statement is satisfied, generating a guard code by applying an if-conversion method to the conditional statement, and converting a guard by using an instruction calculating the guard of the guard code, the instruction calculating the guard using a register where information related to a period of time corresponding to the number of iterations of the inner-most loop is stored. | 09-25-2008 |
20090217249 | COMPILING METHOD AND PROCESSOR USING THE SAME - A compiling method and a processor using the same are provided. The compiling method includes simulating a first program code which includes at least one first operation command to generate a first operation result, compiling the first program code to generate a second program code which includes at least one second operation command, simulating the second program code to generate a second operation result, and comparing the first operation result with the second operation result to verify whether the second program code is valid. | 08-27-2009 |
Patent application number | Description | Published |
20120299077 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point. | 11-29-2012 |
20140179096 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point. | 06-26-2014 |
Patent application number | Description | Published |
20110286270 | SEMICONDUCTOR MEMORY DEVICE AND AN OPERATING METHOD THEREOF - A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a memory controller configured to provide the flash memory with a read address that identifies sectors to be read. The flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence. In addition, the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing. | 11-24-2011 |
20130036261 | METHOD FOR OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM INCLUDING THE SAME - A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by using the first RTC value read from the non-volatile memory and a second RTC value indicating a time-of-day when a read operation is performed, when the read operation for the data programmed to the storage region is performed, and decreasing a maximum count of a read retry operation by using the information, when the read retry operation is performed for the storage region. | 02-07-2013 |
20130080858 | METHOD OF READING DATA FROM A NON-VOLATILE MEMORY AND DEVICES AND SYSTEMS TO IMPLEMENT SAME - Methods of performing a read retry, including reading a non-volatile memory with new read parameters, and devices for performing such methods are disclosed. The read retry operation and/or subsequent read retry operation may be initiated and/or completed before it is determined that such read retry operation is warranted. For example, a page of a NAND flash memory may be read in a read retry operation with new read voltage levels applied to a word line of the page. For example, a read retry operation may be performed on a target page prior to determining errors of a previous read page of data of the target page are uncorrectable via an ECC operation. | 03-28-2013 |
20130128663 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method for programming a non-volatile memory device includes: providing a non-volatile memory device including data cells capable of storing N-bit data (N is a natural number) and a monitoring cell capable of monitoring whether the N-bit data has been programmed into the data cells; performing a first programming operation for the data cells while inhibiting programming of the monitoring cell; and performing a second programming operation for the monitoring cell while inhibiting programming of the data cells, wherein the second programming operation is performed differently from the first programming. | 05-23-2013 |
20130135932 | NON-VOLATILE MEMORY, METHOD OF OPERATING THE SAME, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SYSTEM - A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device. | 05-30-2013 |
20130185612 | FLASH MEMORY SYSTEM AND READ METHOD OF FLASH MEMORY SYSTEM - A read method in a flash memory system containing a flash memory and a memory controller includes updating a selected one of indexes of a selected one of blocks of the flash memory, in a wear-out table for indexing each of the blocks of the flash memory, and setting a start read level to start read retry on the selected block by referring to a read retry table corresponding to a wear-out degree included in the selected index when a current request of read retry on the selected block is received. | 07-18-2013 |
20130326119 | STORAGE DEVICE HAVING NONVOLATILE MEMORY DEVICE AND WRITE METHOD - Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit. | 12-05-2013 |
20130326312 | STORAGE DEVICE INCLUDING NON-VOLATILE MEMORY DEVICE AND REPAIR METHOD - Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block. | 12-05-2013 |
20140204672 | MEMORY SYSTEM - A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks. | 07-24-2014 |
20150070997 | NON-VOLATILE MEMORY, METHOD OF OPERATING THE SAME, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SYSTEM - A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device. | 03-12-2015 |
Patent application number | Description | Published |
20090052241 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node. | 02-26-2009 |
20090067254 | NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING A MULTI LEVEL CELL IN THE SAME - A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 03-12-2009 |
20110026325 | METHOD OF PROGRAMMING A MULTI LEVEL CELL - A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 02-03-2011 |
20140063950 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and configured to sense current flow through the even bit line in response to an even bit line control signal and an even discharge signal. The semiconductor device further includes a second sensing circuit coupled to an odd bit line and configured to sense current flow through the odd bit lines in response to an odd bit line control signal and an odd discharge signal. The first sensing circuit and second sensing circuit are configured to supply a ground voltage to the odd bit line when sensing the current flow through the even bit line, and to supply the ground voltage to the even bit line when sensing the current flow through the odd bit line. | 03-06-2014 |
Patent application number | Description | Published |
20130079248 | FLUID CONTROLLING APPARATUS AND FILTER AND BIOCHIP INCLUDING THE FLUID CONTROLLING APPARATUS - A fluid controlling apparatus including an inlet through which a fluid is introduced, a channel portion connected to the inlet, an outlet that is connected to the channel portion and through which the fluid is discharged, and at least one fluid resisting portion disposed between the inlet and the outlet, as well as a filter and a biochip including the fluid controlling apparatus. | 03-28-2013 |
20130086998 | FLUID CONTROLLING APPARATUS AND METHOD OF CONTROLLING FLUID BY USING THE SAME - A fluid controlling apparatus including at least one sample chamber for holding a fluid containing target materials; a cleaning chamber for holding a cleaning solution; a first multi-port connected to the at least one sample chamber through a first channel and connected to the cleaning chamber through a second channel; a filter portion, connected to the first multi-port through a third channel, for filtering the target materials; and a first pump, connected to the filter portion, for applying a pressure; and a method of controlling a fluid using the fluid controlling apparatus, which comprises passing the fluid containing the target materials from the at least one sample chamber to the filter portion; and cleaning a path of the fluid by passing the cleaning solution through the path. | 04-11-2013 |
20130149217 | CELL CAPTURING FILTER HAVING HIGH ASPECT RATIO - A cell capturing filter, in which cells or particles having a predetermined size or greater in a sample may be easily captured, and clogging of a flow passage due to the captured cells or particles may be prevented, and stresses acting on the captured cells or particles may be reduced, having a first surface and a second substrate having a second surface that is bonded to the first surface, wherein the first substrate may include a flow passage formed in the first surface of the first substrate so that a sample flows in the flow passage, and a barrier that protrudes across the flow passage, and the second substrate may include a fine groove formed in an area on the second surface corresponding to the barrier, and a gap may exist between a surface of the barrier and the fine groove. | 06-13-2013 |
20130149774 | COLLECTIVE CELL COUNTER SYSTEM - A cell counter system includes an inlet via which a fluid containing a plurality of cells inflows; a channel in which the fluid flows; a valve unit, which controls flow of the fluid in the channel; an electrode unit, which is arranged in the channel for measuring impedance for counting a number of the plurality of cells; and an outlet, which is connected to the channel to drain the fluid. | 06-13-2013 |
20130178543 | BIOMARKER FOR DIAGNOSING CANCER AND METHOD OF ISOLATING CANCER CELL USING THE SAME - A method of detecting a cancer stem cell or circulating tumor cell that has undergone epithelial-mesenchymal transition, comprising determining the level of caveolin-1 expressed by a sample cell, and comparing the level of caveolin-1 expressed by the sample cell to a control, wherein higher expression of caveolin-1 by the sample cell indicates that the sample cell is a cancer cell, as well as a method of detecting cancer or metastasis in a subject, and related methods and compositions. | 07-11-2013 |
20130264295 | FILTER FOR CAPTURING TARGET MATERIAL - A target material capturing filter is described herein. The target material capturing filter may include an inlet through which a fluid enters; an outlet through which at least a portion of the fluid is discharged; a first flow path that is connected to the inlet; a second flow path that is connected to the outlet; and a filter unit that is disposed between the first flow path and the second flow path and captures the target material by letting drop at least a portion of the fluid that flows through the first flow path. | 10-10-2013 |
20150034134 | ROLL TYPE FILTER CLEANING APPARATUS - Provided is a filter cleaning apparatus for cleaning a roll-type filter including a cleaning tank with a cavity for accommodating a cleaning solution, and a frame that is separable from the cleaning tank and is provided with a fixed portion for fixing a roll-type filter and a supporting portion for supporting weight of the roll-type filter, wherein the supporting portion includes a plurality of through holes through which the cleaning solution passes, and a plurality of supporting members for partially supporting a lower portion of the roll-type filter. | 02-05-2015 |
20150147769 | METHOD OF TESTING SAMPLE AND MICROFLUIDIC DEVICE - A method of testing a sample to determine a concentration of a target material included in the sample and a microfluidic device in which a reaction of the sample and a reagent occurs are provided. The method includes mixing a sample with a reagent that changes optical characteristics in accordance with a concentration of chlorine ions in the sample, and a capturing material that captures some of the chlorine ions in the sample; measuring the optical characteristics after mixing the sample with the reagent and the capturing material; and determining a concentration of the chlorine ions in the sample based on the measured optical characteristics. | 05-28-2015 |
Patent application number | Description | Published |
20110189608 | PHOTORESIST COMPOSITION FOR FABRICATING PROBE ARRAY, METHOD OF FABRICATING PROBE ARRAY USING THE PHOTORESIST COMPOSITION, COMPOSITION FOR PHOTOSENSITIVE TYPE DEVELOPED BOTTOM ANTI-REFLECTIVE COATING, FABRICATING METHOD OF PATTERNS USING THE SAME AND FABRICATING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME - A photoresist composition for fabricating a probe array is provided. The photoresist composition includes a photoacid generator having an onium salt and an i-line reactive sensitizer. | 08-04-2011 |
20110201528 | Methods Of Forming An Oligomer Array - The present invention provides compositions for forming an oligomer array and methods for using the same. Such a composition may include an acid stable polymer, a photoacid generator and an organic solvent and may allow for the selective attachment of oligormers at one or more desired positions on a substrate using long wavelength light. | 08-18-2011 |
20110244397 | Methods of Fabricating a Microarray - A method of fabricating a microarray is provided, which includes providing a substrate having a surface that is protected by an acid labile protective group that includes an acetal group represented by formula (1) and has a functional group that can be coupled with a monomer of a probe; applying a photoresist including a photo acid generator to the substrate; selectively exposing the photoresist to deprotect the acid labile protective group that corresponds to an exposed region; removing the photoresist; and coupling the monomer that is combined with the acid labile protective group with the deprotected functional group. Formula (1) has the following structure: | 10-06-2011 |
20150243525 | METHOD OF FORMING A FINE PATTERN BY USING BLOCK COPOLYMERS - A method of forming a fine pattern includes forming a phase separation guide layer on a substrate, forming a neutral layer on the phase separation guide layer, forming a first pattern including first openings on the neutral layer, forming a second pattern including second openings each having a smaller width than each of the first openings, forming a neutral pattern including guide patterns exposing a portion of the phase separation guide layer by etching an exposed portion of the neutral layer by using the second pattern as an etch mask, removing the second pattern to expose a top surface of the neutral pattern, forming a material layer including a block copolymer on the neutral pattern and the phase separation guide layer exposed through the guide patterns, and forming a fine pattern layer including a first block and a second block on the neutral pattern and the phase separation guide layer. | 08-27-2015 |
Patent application number | Description | Published |
20140211103 | DISPLAY DEVICE - Touch-related information which cannot be acquired by the naked eye (dubbed here as sub-optical pattern information) has its corresponding sub-optical patterns respectively positioned within the aperture areas of respective domains such that the displayed image, as viewed from different viewing angles is not adversely affected by the embedded sub-optical patterns. One type of touch-related information which can be conveyed is that of touch location of a sub-optical pattern sensing pen positioned over one or more of the sub-optical patterns. | 07-31-2014 |
20150228240 | GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME - A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage. | 08-13-2015 |
20150236161 | THIN FILM TRANSISTOR - A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value. | 08-20-2015 |
20150277200 | DISPLAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME - A display substrate includes a thin film transistor array disposed in a display area, a signal line disposed in a peripheral area surrounding the display area, a contact electrode disposed on the signal line and contacting the signal line, a light-blocking pattern overlapping a first portion of the contact electrode, and a color pattern overlapping a second portion of the contact electrode. | 10-01-2015 |
Patent application number | Description | Published |
20130339988 | APPARATUS FOR PROTECTING OPTICAL DISC DRIVES - Provided are apparatuses for grounding the objective lens driving unit of an optical pickup device. An optical pickup device includes an objective lens driving unit and a base that supports the objective lens driving unit, and wherein the objective lens driving unit includes a moving structure including an objective lens and a plurality of drive coils; a static structure comprising magnets corresponding to the plurality of drive coils, a yoke that supports the magnets, and a wire holder that has a plurality of wiring layers including a ground wiring layer; a plurality of suspension wires that connect the plurality of drive coils to the plurality of wiring layers; a supporting portion connected to the yoke and fixed to the wire holder; a projection extending from the supporting portion and disposed adjacent to the ground wiring layer; and conductive bonding material connects the ground wiring layer with the projection. | 12-19-2013 |
20140053169 | OBJECT LENS DRIVING DEVICE AND OPTICAL DISC DRIVE INCLUDING THE SAME - Provided is an object lens driving device that includes a wire holder coupled to a support portion and on which an end of a plurality of suspension wires are fixed. The wire holder includes a first area supported on the support portion and a second area extending from the first area and on which the end of each of the plurality of suspension wires is fixed. In this example, a thickness of the second area is thinner than a thickness of the first area. | 02-20-2014 |
20140325536 | OBJECTIVE LENS DRIVING UNIT AND OPTICAL DISC DRIVE USING THE SAME - Provided is an objective lens driving unit in which a wire holder is coupled to a circuit board. In a conventional objective lens driving unit, a connection between a wire holder and a circuit board may deteriorate over time due to a deterioration of the connection. According to various aspects, a wire holder may be directly coupled to a circuit board by insert molding, thus improving the connection between the wire holder and the circuit board over time. | 10-30-2014 |
Patent application number | Description | Published |
20130157428 | Methods of Manufacturing Semiconductor Devices Including Transistors - A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern. | 06-20-2013 |
20140035058 | Semiconductor Devices and Methods of Manufacturing the Same - Methods of manufacturing a semiconductor device include forming a thin layer on a substrate including a first region and a second region and forming a gate insulating layer on the thin layer. A lower electrode layer is formed on the gate insulating layer and the lower electrode layer disposed in the second region is removed to expose the gate insulating layer in the second region. Nitrogen is doped into an exposed portion of the gate insulating layer and the thin layer disposed under the gate insulating layer. An upper electrode layer is formed on the lower electrode layer remaining in the first region and the exposed portion of the gate insulating layer. The upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer are partially removed to form first and second gate structures in the first and second regions. The process may be simplified. | 02-06-2014 |
20140291755 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode. | 10-02-2014 |
20150132937 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge). | 05-14-2015 |
20150228722 | SEMICONDUCTOR DEVICE INCLUDING FIN-TYPE FIELD EFFECT TRANSISTOR - Provided is a semiconductor device including: a substrate; a first fin-field effect transistor comprising a first fin-type semiconductor layer having a first height and a first width, formed on the substrate; and a second fin-field effect transistor comprising a second fin-type semiconductor layer having a second height and a second width, formed on the substrate. The first fin-field effect transistor and the second fin-field effect transistor are separated by a predetermined distance. The first height is greater than the second height and the first width is less than the second width. | 08-13-2015 |