Patent application number | Description | Published |
20080270682 | METHOD FOR USING A MULTI-BIT CELL FLASH DEVICE IN A SYSTEM NOT DESIGNED FOR THE DEVICE - A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method. | 10-30-2008 |
20080286082 | METHODS AND SYSTEMS FOR INTERRUPTED COUNTING OF ITEMS IN COUNTAINERS - Methods and systems for counting items in storage containers in an array of at least two storage containers, the method including the steps of: providing a storage array of at least two storage containers, each of the storage containers containing an unknown amount of items; providing a receiving array of at least two receiving containers, wherein the receiving containers initially contain no items; extracting a layer of the items from the storage array; inserting the layer into corresponding locations in the receiving array; repeating the steps of extracting and inserting while at least one of the storage containers is not empty; counting, for each storage container in the storage array, a productive-extraction amount; and reporting, for at least some of the storage containers, the productive-extraction amount from each storage container. Preferably, the method further includes recovering a storage identity upon recovery from a system failure that erases the productive-extraction amount. | 11-20-2008 |
20090113146 | SECURE PIPELINE MANAGER - A method for data storage includes supplying data to and from a host to a storage memory via a secure data path. A first CPU is employed to control operation of the storage memory, and a second CPU is employed to control operation of the secure data path. | 04-30-2009 |
20090263935 | RECYCLING FAULTY MULTI-DIE PACKAGES - The present invention teaches the recycling of a faulty multi-die memory package by isolating the functional part of the package and using it as a smaller memory package. | 10-22-2009 |
20090319843 | METHOD AND APPARATUS FOR ERROR CORRECTION - Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, after an attempt is made to write original data to a ‘target’ memory, data is read back from the target memory in a ‘first read operation’, thereby generating first read data. After the first read operation, the first read data is compared to the original data and/or an indication of a difference between the original data and the first data is determined. The information obtained by effecting the data-comparison and/or information related to the difference indication is used when correcting errors in data read back from the target memory in a ‘second read operation.’. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM. | 12-24-2009 |
20100199135 | METHOD, SYSTEM AND COMPUTER-READABLE CODE TO TEST FLASH MEMORY - A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die. | 08-05-2010 |
20110114738 | AUTOMATED CARD CUSTOMIZATION MACHINE - A memory card includes a non-volatile memory, a connector configured to enable the memory card to be operatively coupled to a host computer, and a housing enclosing the non-volatile memory. The housing has a customized physical contour that is determined according to a user-selected value. | 05-19-2011 |
20120233385 | HARD DISK DRIVE WITH OPTIONAL CACHE MEMORY - A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably connectable to a cache memory. The processor is adapted, subsequent to an initial interrogation of the cache interface, to determine whether the cache memory is connected to the cache interface by inspecting an indication of the presence or the absence of the cache memory, the indication being stored in a register in the processor or in a memory associated with the processor such that the inspecting avoids repeat interrogation of the cache interface, to communicate with the cache memory and the hard disk drive such that the processor has access to the cache memory when the cache memory is connected to the cache interface, and to communicate with the hard disk drive when the cache memory is disconnected from the cache interface. | 09-13-2012 |
20120243654 | Methods for Interrupted Counting of Particles in Cells - A method executed by a circuit for counting electrons in storage cells in an array of at least two storage cells is provided. The method includes providing a storage array of at least two storage cells, and each of said at least two storage cells containing an unknown amount of electrons. A receiving array of at least two receiving cells is provided, where said at least two receiving cells initially contain no electrons. Then, extracting a layer of said electrons from said storage array of cells and inserting said layer into corresponding locations in said receiving array. The method then repeats said steps of extracting and inserting while at least one of said at least two storage cells is not empty. The method counts, for each said storage cell in said storage array, a productive-extraction amount. | 09-27-2012 |
20140143482 | MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES - A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. | 05-22-2014 |
20140143483 | MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES - A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. | 05-22-2014 |