Patent application number | Description | Published |
20110010484 | OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY - During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages. | 01-13-2011 |
20110099460 | Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced. | 04-28-2011 |
20110149650 | Data Transfer Flows for On-Chip Folding - A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations. | 06-23-2011 |
20110153911 | METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING - A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die. | 06-23-2011 |
20110153913 | Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data - A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host. | 06-23-2011 |
20130170293 | HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES - A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC. | 07-04-2013 |
20150124527 | Detecting Programmed Word Lines Based On NAND String Current - A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block. | 05-07-2015 |
Patent application number | Description | Published |
20130128666 | Scrub Techniques for Use with Dynamic Read - The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected. | 05-23-2013 |
20130205066 | ENHANCED WRITE ABORT MANAGEMENT IN FLASH MEMORY - A memory system or flash card may include safe zone blocks where data is written in case of an error condition, such as a write abort. The system may utilize predetermined risk zones when selecting the data that is written to the safe zone blocks. For example, data written to a lower page may be one example of data that is a predetermined risk. Upon receiving a write command, the data that is written to a lower page may be written to a safe zone either in parallel or after the write operation. | 08-08-2013 |
20140173172 | SYSTEM AND METHOD TO UPDATE READ VOLTAGES IN A NON-VOLATILE MEMORY IN RESPONSE TO TRACKING DATA - A method includes reading a representation of tracking data from at least a portion of a non-volatile memory. The method further includes adjusting a read voltage based on a comparison between a number of bits in tracking data as compared to a count of bits in the representation of the tracking data. | 06-19-2014 |
20140173382 | INSPECTION OF NON-VOLATILE MEMORY FOR DISTURB EFFECTS - A method performed in a data storage device including a non-volatile memory includes reading a representation of data, the representation corresponding to one or more selected states of storage elements of a group of storage elements of the non-volatile memory. The method includes, in response to a count of errors in the representation of the data exceeding a threshold, scheduling a remedial action to be performed on the group of storage elements. | 06-19-2014 |
20140247660 | Compensation for Sub-Block Erase - A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme. | 09-04-2014 |
20140247665 | Select Transistor Tuning - In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range. | 09-04-2014 |
20140250266 | Data Randomization in 3-D Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings. | 09-04-2014 |
20140269052 | SYSTEM AND METHOD OF DETERMINING READING VOLTAGES OF A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique. | 09-18-2014 |
20140281250 | Systems and Methods for Performing Data Recovery in a Memory System - Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page. | 09-18-2014 |
20140281682 | Systems and Methods for Performing Defect Detection and Data Recovery in a Memory System - Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system may receive a command to write data in a memory of the memory system; determine a physical location of the memory that is associated with the data write; write data associated with the data write to the physical location; and store the physical location of the memory that is associated with the data write in a Tag cache. The controller may further identify a data keep cache of a plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write; update an XOR sum based on the data of the data write; and store the updated XOR sum in the identified data keep cache. | 09-18-2014 |
20140281685 | PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line. | 09-18-2014 |
20140281766 | PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line. | 09-18-2014 |
20140351496 | Optimized Configurable NAND Parameters - Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array. | 11-27-2014 |
20140355345 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 12-04-2014 |
20140359400 | Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block. | 12-04-2014 |
20140369122 | PSEUDO BLOCK OPERATION MODE IN 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 12-18-2014 |
20140369123 | PSEUDO BLOCK OPERATION MODE IN 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 12-18-2014 |
20150046770 | SENSING PARAMETER MANAGEMENT IN NON-VOLATILE MEMORY STORAGE SYSTEM TO COMPENSATE FOR BROKEN WORD LINES - Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line. | 02-12-2015 |
20150063028 | Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors. | 03-05-2015 |
20150071008 | Systems And Methods For Read Disturb Management In Non-Volatile Memory - Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles. | 03-12-2015 |
20150082120 | Selective In-Situ Retouching of Data in Nonvolatile Memory - In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge. | 03-19-2015 |
20150085574 | Back Gate Operation with Elevated Threshold Voltage - In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming. | 03-26-2015 |
20150092493 | Pseudo Block Operation Mode In 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 04-02-2015 |
20150117099 | Selection of Data for Redundancy Calculation By Likely Error Rate - Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. | 04-30-2015 |
20150121156 | Block Structure Profiling in Three Dimensional Memory - Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes. | 04-30-2015 |
20150121157 | Selection of Data for Redundancy Calculation By Likely Error Rate - Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. | 04-30-2015 |
20150134885 | Identification and Operation of Sub-Prime Blocks in Nonvolatile Memory - In a block-erasable nonvolatile memory array, blocks are categorized as bad blocks, prime blocks, and sub-prime blocks. Sub-prime blocks are identified from their proximity to bad blocks or from testing. Sub-prime blocks are configured for limited operation (e.g. only storing non-critical data, or data copied elsewhere, or using some additional or enhanced redundancy scheme). | 05-14-2015 |
20150143025 | Update Block Programming Order - Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time. | 05-21-2015 |
20150143030 | Update Block Programming Order - Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time. | 05-21-2015 |
20150160857 | Lower Page Only Host Burst Writes - In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage. | 06-11-2015 |
20150160893 | Lower Page Only Host Burst Writes - In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage. | 06-11-2015 |
20150162086 | Systems and Methods for Partial Page Programming of Multi Level Cells - Multiple bits of data are programmed together to each cell of a segment of a word line while other segments of the same word line are unprogrammed. Subsequently, additional segments are similarly programmed. Data is read from a partially programmed word line (with a mix of programmed and unprogrammed segments) using a single reading scheme. | 06-11-2015 |
20150162087 | WRITE SCHEME FOR CHARGE TRAPPING MEMORY - In a charge trapping memory, data that would otherwise be likely to remain adjacent to unwritten word lines is written three times, along three immediately adjacent word lines. The middle copy is protected from charge migration on either side and is considered a safe copy for later reading. Dummy data may be programmed along a number of word lines to format a block for good data retention. | 06-11-2015 |
20150162088 | String Dependent Parameter Setup - In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone. | 06-11-2015 |
20150331626 | In-Situ Block Folding for Nonvolatile Memory - In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation. | 11-19-2015 |
20160026410 | Weighted Read Scrub for Nonvolatile Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced. | 01-28-2016 |
20160055918 | Zoned Erase Verify in Three Dimensional Nonvolatile Memory - In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data. | 02-25-2016 |
Patent application number | Description | Published |
20120284574 | Non-Volatile Memory and Method Having Efficient On-Chip Block-Copying with Controlled Error Rate - A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget. | 11-08-2012 |
20140029342 | EXPERIENCE COUNT DEPENDENT PROGRAM ALGORITHM FOR FLASH MEMORY - In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages. | 01-30-2014 |
20140075252 | Erased Page Confirmation in Multilevel Memory - In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition. | 03-13-2014 |
20140095770 | Selective Protection of Lower Page Data During Upper Page Write - Lower page data that may be endangered by programming upper page data in the same memory cells is protected during upper programming using protective upper page programming schemes. High overall programming speeds are maintained by selectively using protective upper programming schemes only where endangered data is committed and may not be recoverable from another location. | 04-03-2014 |
20140098610 | Erased State Reading - Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the conventional read does not indicate partial programming, performs a second read using lower read-pass voltage on at least one neighboring word line. | 04-10-2014 |
20140115230 | Flash Memory with Data Retention Partition - A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data. | 04-24-2014 |
20140126292 | Flash Memory with Data Retention Bias - Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die. | 05-08-2014 |
20140133232 | Compensation for Sub-Block Erase - A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme. | 05-15-2014 |
20140146609 | Weighted Read Scrub For Nonvolatile Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced. | 05-29-2014 |
20140149641 | Optimized Configurable NAND Parameters - Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array. | 05-29-2014 |
20140153333 | Systems and Methods to Avoid False Verify and False Read - In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells. | 06-05-2014 |
20140160842 | Adaptive Operation of Multi Level Cell Memory - A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode. | 06-12-2014 |
20140164679 | Dynamic Block Linking with Individually Configured Plane Parameters - A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors. | 06-12-2014 |
20140169095 | Select Transistor Tuning - In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range. | 06-19-2014 |
20140215126 | Data Randomization in 3-D Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings. | 07-31-2014 |
20140254263 | Write Sequence Providing Write Abort Protection - In a multi-level cell (MLC) nonvolatile memory array, data is assigned sequentially to the lower and upper page of a word line, then both lower and upper pages are programmed together before programming a subsequent word line. Word lines of multiple planes are programmed together using latches to hold data until all data is transferred. Tail-ends of data of write commands are stored separately. | 09-11-2014 |
20140281141 | Binning of Blocks for Dynamic Linking - A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors. | 09-18-2014 |
20140355344 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 12-04-2014 |
20140359398 | Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block. | 12-04-2014 |
20150067419 | Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors. | 03-05-2015 |