Patent application number | Description | Published |
20110252187 | SYSTEM AND METHOD FOR OPERATING A NON-VOLATILE MEMORY INCLUDING A PORTION OPERATING AS A SINGLE-LEVEL CELL MEMORY AND A PORTION OPERATING AS A MULTI-LEVEL CELL MEMORY - System and method for storing data in a non-volatile memory including a multi-level cell and single-level cell memory portions. To write a dataset to the non-volatile memory, if the size of the dataset is equal to the size of pages in the multi-level cell memory portion, the dataset may be written directly to the multi-level cell memory portion to fill an integer number of pages in a single write operation. However, if the size of the dataset is different than the size of the multi-level cell memory pages, at least a portion of the dataset may be temporarily written to the single-level cell memory portion until data is accumulated in a plurality of write operations having a size equal the size of the multi-level cell memory pages. The accumulated data may fill an integer number of the pages in the multi-level cell memory portion in a single write operation. | 10-13-2011 |
20110271043 | SYSTEM AND METHOD FOR ALLOCATING AND USING SPARE BLOCKS IN A FLASH MEMORY - A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool. | 11-03-2011 |
20120001778 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING - A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data. | 01-05-2012 |
20120005554 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING - A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values. | 01-05-2012 |
20120005558 | SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES - A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level. | 01-05-2012 |
20120005560 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING - A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful. | 01-05-2012 |
20120144093 | INTERLEAVING CODEWORD PORTIONS BETWEEN MULTIPLE PLANES AND/OR DIES OF A FLASH MEMORY DEVICE - A system, a method and non-transitory computer readable medium storing instructions for interleaving at least two portions of a first codeword of the group between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule and interleaving different portions of other codewords of the group between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. | 06-07-2012 |
20130212315 | STATE RESPONSIVEOPERATIONS RELATING TO FLASH MEMORY CELLS - A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state. | 08-15-2013 |