Patent application number | Description | Published |
20090279207 | THIN-FILM MAGNETIC HEAD, METHOD OF MANUFACTURING THE SAME, HEAD GIMBAL ASSEMBLY, AND HARD DISK DRIVE - A thin-film magnetic head is constructed such that a main magnetic pole layer having a magnetic pole end face on a side of a medium-opposing surface opposing a recording medium, a write shield layer opposing the main magnetic pole layer on the medium-opposing surface side, a gap layer formed between the main magnetic pole layer and write shield layer, and a thin-film coil wound about the write shield layer or main magnetic pole layer are laminated on a substrate. This thin-film coil has a plurality of turn parts arranged at respective positions having different distances from the medium-opposing surface, while a non-expandable part made of an insulating material having a coefficient of thermal expansion smaller than that of a photosensitive resin is formed between the turn parts. | 11-12-2009 |
20090296275 | THIN-FILM MAGNETIC HEAD, METHOD OF MANUFACTURING THE SAME, HEAD GIMBAL ASSEMBLY, AND HARD DISK DRIVE - A thin-film magnetic head is constructed such that a main magnetic pole layer having a magnetic pole end face on a side of a medium-opposing surface opposing a recording medium, a write shield layer opposing the main magnetic pole layer on the medium-opposing surface side, a gap layer formed between the main magnetic pole layer and write shield layer, and a thin-film coil wound about the write shield layer or main magnetic pole layer are laminated on a substrate. This thin-film magnetic head has an equidistant two-stage structure in which a first turn part of a first conductor layer and a second turn part of a second conductor layer overlap vertically along the medium-opposing surface while having the same front distance from respective front side faces closer to the medium-opposing surface to the medium-opposing surface. | 12-03-2009 |
20100192343 | METHOD OF MANUFACTURING CERAMIC CAPACITOR - In a method of manufacturing ceramic capacitor according to the present invention, a pair of interdigitated internal electrodes are arranged perpendicularly to the surface of the substrate, subsequent to which the respective end faces of this pair of internal electrodes are exposed, and a pair of external electrodes are formed at these exposed end faces. In this method of manufacturing ceramic capacitor, formation of the external electrodes on the end faces of the respective internal electrodes, with these internal electrodes being interdigitately integrally-formed and the end faces thereof being exposed, it possible to reliably and easily form the external electrodes. | 08-05-2010 |
20100195264 | CERAMIC CAPACITOR AND METHOD OF MANUFACTURING SAME - In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out. | 08-05-2010 |
20110068456 | Layered chip package and method of manufacturing same - A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires. | 03-24-2011 |
20110095289 | Laminated chips package, semiconductor substrate and method of manufacturing the laminated chips package - In a laminated chip package, a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device are laminated. On a side surface for wiring of the laminated chip package, an end face of an inner electrode for examination formed inside the side surface for wiring in the semiconductor plate is formed. The laminated chip package further has an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates. | 04-28-2011 |
20110095414 | Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same - A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer. The semiconductor substrate can be manufactured by forming a plurality of groove portions along scribe lines; applying an insulating material to a surface on a side where the plurality of groove portions are formed to form a surface insulating layer; and forming a wiring electrode connected to the semiconductor device and in a protruding shape rising above a surface of the surface insulating layer, after the formation of the surface insulating layer. | 04-28-2011 |
20110096435 | Heat-assisted magnetic recording head with laser diode fixed to slider - A heat-assisted magnetic recording head includes a slider, an edge-emitting laser diode fixed to the slider, and an external mirror fixed to the laser diode. The laser diode has an emitting end face that includes an emission part for emitting laser light; a mounting surface that lies at an end in a direction perpendicular to the plane of an active layer and faces the slider; and a rear surface opposite to the mounting surface. The external mirror includes: a first to-be-fixed part disposed along the emitting end face; a second to-be-fixed part disposed along the rear surface; and a coupling part that couples the first and second to-be-fixed parts to each other. The first to-be-fixed part has a reflecting surface that reflects the laser light emitted from the emission part toward the waveguide. | 04-28-2011 |
20110180932 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed. | 07-28-2011 |
20110186985 | Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same - A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof. | 08-04-2011 |
20110189820 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other. | 08-04-2011 |
20110189822 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies. | 08-04-2011 |
20110228417 | HEAT-ASSISTED MAGNETIC RECORDING HEAD WITH NEAR-FIELD LIGHT GENERATING ELEMENT - A near-field light generating element has an outer surface. The outer surface includes a bottom surface, first and second inclined surfaces, an edge part that connects the first and second inclined surfaces to each other, and a front end face located in a medium facing surface. The front end face includes a first side that lies at an end of the first inclined surface, a second side that lies at an end of the second inclined surface, and a tip that is formed by contact of the first and second sides with each other and forms a near-field light generating part. Each of the first side and the second side has a lower part and an upper part that are continuous with each other. An angle formed between the upper part of the first side and the upper part of the second side is smaller than that formed between the lower part of the first side and the lower part of the second side. | 09-22-2011 |
20110228418 | HEAT-ASSISTED MAGNETIC RECORDING HEAD WITH NEAR-FIELD LIGHT GENERATING ELEMENT - A near-field light generating element has an outer surface including a bottom surface that lies at an end closer to a top surface of a substrate, a waveguide facing surface that lies at an end farther from the top surface of the substrate and faces a waveguide, a front end face located in a medium facing surface, and a side surface that connects the bottom surface, the waveguide facing surface and the front end face to each other. The front end face includes a first side that lies at an end of the bottom surface, a tip that lies at an end farther from the top surface of the substrate and forms a near-field light generating part, a second side that connects an end of the first side to the tip, and a third side that connects the other end of the first side to the tip. The waveguide facing surface includes a width changing portion that has a width in a direction parallel to the bottom surface and the front end face, the width decreasing with decreasing distance to the front end face. | 09-22-2011 |
20110241480 | Surface acoustic wave device - A surface acoustic wave device according to the present invention includes a piezoelectric monocrystal substrate | 10-06-2011 |
20110266692 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole. | 11-03-2011 |
20110316141 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip. | 12-29-2011 |
20120013024 | Layered Chip Package and Method of Manufacturing Same - A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip. | 01-19-2012 |
20120013025 | Layered Chip Package and Method of Manufacturing Same - A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip. The plurality of wires include a plurality of common wires and a plurality of layer-dependent wires. In at least one of the layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires. | 01-19-2012 |
20120025355 | LAMINATED SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole. | 02-02-2012 |
20120032318 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other. | 02-09-2012 |
20120056333 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion. | 03-08-2012 |
20120080782 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires. | 04-05-2012 |
20120086130 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion. | 04-12-2012 |
20120126427 | MEMORY DEVICE, LAMINATED SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip. | 05-24-2012 |
20120142146 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires. | 06-07-2012 |
20120147499 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING WITH SHIELD AROUND MAIN POLE - A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section is magnetically connected to the bottom shield and is greater than the bottom shield in length in a direction perpendicular to the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other. The coil includes a first portion that passes through a space defined by the main pole and the first return path section, and a second portion that passes through a space defined by the main pole and the second return path section. | 06-14-2012 |
20120147500 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING HAVING A TAPERED MAIN POLE - A bottom end of a main pole includes first, second, and third portions that are contiguously arranged in order of increasing distance from the medium facing surface. A top surface of the main pole includes fourth, fifth, and sixth portions that are contiguously arranged in order of increasing distance from the medium facing surface. A distance from the top surface of the substrate to any given point on each of the first and second portions decreases with increasing distance from the given point to the medium facing surface. The second portion has an angle of inclination greater than that of the first portion with respect to a direction perpendicular to the medium facing surface. A distance from the top surface of the substrate to any given point on each of the fourth and fifth portions increases with increasing distance from the given point to the medium facing surface. The fifth portion has an angle of inclination greater than that of the fourth portion with respect to the direction perpendicular to the medium facing surface. | 06-14-2012 |
20120147501 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING WITH SHIELD AROUND MAIN POLE - A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section includes a yoke layer, and first and second coupling layers that magnetically couple the bottom shield and the yoke layer to each other. The first coupling layer is magnetically connected to the bottom shield. The second coupling layer magnetically couples the first coupling layer to the yoke layer. No end faces of the second coupling layer are exposed in the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other. | 06-14-2012 |
20120170156 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING HAVING A MAIN POLE AND TWO SHIELDS - A magnetic head includes: a coil; a main pole; a first shield disposed backward of the main pole along a direction of travel of a recording medium; a first return path section connecting the first shield to the main pole; a second shield disposed forward of the main pole along the direction of travel of the recording medium; and a second return path section connecting the second shield to the main pole. An interface between the first return path section and the main pole has an end closest to a medium facing surface, and an interface between the second return path section and the main pole has an end closest to the medium facing surface, the latter being closer to the medium facing surface than the former. The second return path section includes a yoke layer located away from the medium facing surface and in contact with the main pole. The coil includes at least one coil element that passes between the second shield and the yoke layer. | 07-05-2012 |
20120187575 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes a plurality of common electrodes electrically connected to the plurality of common lines, and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to. | 07-26-2012 |
20120188666 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING HAVING A MAIN POLE AND A SHIELD - A magnetic head includes: a main pole; a coil; a first shield with an end face located in a medium facing surface at a position forward of an end face of the main pole along a direction of travel of a recording medium; a gap part including a portion located between the main pole and the first shield; and a first return path section disposed forward of the main pole along the direction of travel of the recording medium. The first return path section connects the first shield and the main pole to each other so that a first space is defined by the main pole, the gap part, the first shield, and the first return path section. The coil includes a plurality of first coil elements extending to pass through the first space and aligned in a row in the direction of travel of the recording medium. | 07-26-2012 |
20120218662 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING THAT INCLUDES A SENSOR FOR DETECTING CONTACT WITH A RECORDING MEDIUM - A magnetic head for perpendicular magnetic recording includes a read head unit, a write head unit disposed forward of the read head unit along the direction of travel of a recording medium, a heater that generates heat for causing the medium facing surface to protrude in part, an expansion layer that makes part of the medium facing surface protrude, and a sensor that detects contact of the part of the medium facing surface with the recording medium. The write head unit includes a main pole, a write shield, and a return path section. The return path section includes a yoke layer located backward of the main pole along the direction of travel of the recording medium, a first coupling part that couples the yoke layer and the write shield to each other, and a second coupling part that is located away from the medium facing surface and couples the yoke layer and the main pole to each other. | 08-30-2012 |
20120218663 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING THAT INCLUDES A SENSOR FOR DETECTING CONTACT WITH A RECORDING MEDIUM - A magnetic head includes a main pole, a write shield, a return path section, a heater that generates heat for making part of a medium facing surface protrude, and a sensor that detects contact of the part of the medium facing surface with a recording medium. The return path section includes: a yoke layer located backward of the main pole along the direction of travel of the recording medium; a first coupling part coupling the yoke layer and the write shield to each other; and a second coupling part located away from the medium facing surface and coupling the yoke layer and the main pole to each other. The first coupling part has an end face facing toward the yoke layer. This end face includes a middle portion spaced from the yoke layer and facing the yoke layer, and two side portions located on opposite sides of the middle portion in a track width direction and in contact with the yoke layer. The sensor is located between the middle portion and the yoke layer. | 08-30-2012 |
20120256321 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width. | 10-11-2012 |
20120257304 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING HAVING A MAIN POLE AND A SHIELD - A magnetic head includes a coil, a main pole, a write shield, and first and second yoke layers. The first and second yoke layers are magnetically connected to the write shield and aligned along the direction of travel of a recording medium such that the main pole is interposed therebetween. The coil includes a winding portion of planar spiral shape that is formed in one or more layers. The magnetic head further includes: a first coupling part located away from the medium facing surface and magnetically coupling the main pole and the second yoke layer to each other; and a second coupling part located away from the medium facing surface and magnetically coupling the first yoke layer and the second yoke layer to each other without touching the main pole. The winding portion is wound around the first coupling part, and a part of the winding portion passes between the first and second coupling parts. | 10-11-2012 |
20120313259 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines. | 12-13-2012 |
20120313260 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion. | 12-13-2012 |
20120314323 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDINGHAVING A MAIN POLE AND A SHIELD AND SPECIFICALLY STRUCTURED AND LOCATED COIL ELEMENTS AND MAGNETIC COUPLING LAYERS - A magnetic head includes a coil, a main pole, a gap part, a write shield, and a return path section. The return path section includes a yoke part and first and second coupling layers. The first coupling layer is connected to the write shield. The second coupling layer magnetically couples the first coupling layer to the yoke part, and has an end face facing toward a medium facing surface and located away from the medium facing surface. The coil includes a first coil element and a plurality of second coil elements that each extend to pass through a space defined by the main pole, the gap part, the write shield, and the return path section. The first coil element is disposed with the first coupling layer interposed between the medium facing surface and the first coil element. The second coil elements are disposed with the second coupling layer interposed between the medium facing surface and the second coil elements, and with the first coil element interposed between the main pole and the second coil elements. The second coil elements are aligned perpendicularly to the medium facing surface. | 12-13-2012 |
20130020723 | COMPOSITE LAYERED CHIP PACKAGE - A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring. | 01-24-2013 |
20130038966 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDINGHAVING A MAIN POLE, A SHIELD AND A COIL CORE PART SETBACK AWAY FROM THE MEDIUM FACING SURFACE A SPECIFIED DISTANCE - A magnetic head includes: a main pole; a coil; a first shield having an end face that is located in a medium facing surface at a position forward of an end face of the main pole along a direction of travel of a recording medium; and a first return path section disposed forward of the main pole along the direction of travel of the recording medium. The first return path section connects part of the main pole away from the medium facing surface to the first shield so that a first space is defined. The coil includes a first portion having a planar spiral shape and wound around a core part of the first return path section. The first portion includes first and second coil elements that each extend through the first space. No part of the coil other than the first and second coil elements exists in the first space. | 02-14-2013 |
20130075935 | COMPOSITE LAYERED CHIP PACKAGE - A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other. | 03-28-2013 |
20130105949 | LAMINATED SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME | 05-02-2013 |
20130176644 | THIN-FILM MAGNETIC HEAD, METHOD OF MANUFACTURING THE SAME, HEAD GIMBAL ASSEMBLY, AND HARD DISK DRIVE - A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, a thin-film coil and a shield magnetic layer are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. This thin-film magnetic head has a hard guard frame layer surrounding an equidistant coil part, disposed at a position equidistant from the substrate, from outside and being in direct contact with almost a whole outside surface defining an outer shape of the equidistant coil part. | 07-11-2013 |
20130241081 | COMBINATION FOR COMPOSITE LAYERED CHIP PACKAGE - A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip. | 09-19-2013 |
20130279042 | THIN FILM PIEZOELECTRIC ELEMENT AND MANUFACTURING METHOD THEREOF, MICRO-ACTUATOR, HEAD GIMBAL ASSEMBLY AND DISK DRIVE UNIT WITH THE SAME - A thin film piezoelectric element of the present invention includes a substrate and a piezoelectric thin film stack formed on the substrate. The piezoelectric thin film stack includes a top electrode layer, a bottom electrode layer and a piezoelectric layer sandwiched between the top electrode layer and the bottom electrode layer, wherein the piezoelectric layer includes a first piezoelectric layer and a second piezoelectric layer whose compositions have different phase structures. The present invention can obtain high piezoelectric constants, enhanced coercive field strength and good thermal stability, thereby enabling larger applied field strength without depolarization and achieving a large stroke for its applied device. | 10-24-2013 |
20130279044 | THIN FILM PIEZOELECTRIC ELEMENT AND MANUFACTURING METHOD THEREOF, MICRO-ACTUATOR, HEAD GIMBAL ASSEMBLY AND DISK DRIVE UNIT WITH THE SAME - A thin film piezoelectric element of the present invention includes a substrate and a piezoelectric thin film stack formed on the substrate. The piezoelectric thin film stack includes a top electrode layer, a bottom electrode layer and a piezoelectric layer sandwiched between the top electrode layer and the bottom electrode layer, wherein the piezoelectric layer includes a first piezoelectric layer and a second piezoelectric layer whose compositions have different phase structures. The present invention can obtain high piezoelectric constants, enhanced coercive field strength, thereby enabling larger applied field strength without depolarization and achieving a large stroke for its applied device. | 10-24-2013 |
20130308227 | MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING HAVING A MAIN POLE AND A SHIELD - A magnetic head includes a magnetic structure incorporating a write shield. The magnetic structure is formed to include a first magnetic layer, a second magnetic layer stacked on the first magnetic layer, and a seed layer. The first magnetic layer has a front end face located in the medium facing surface and a top surface. The second magnetic layer has a front end face located in the medium facing surface and a bottom surface. The top surface of the first magnetic layer includes a first region including an end located in the medium facing surface and a second region farther from the medium facing surface than the first region. The seed layer is not present on the first region of the top surface of the first magnetic layer but is present on the second region. | 11-21-2013 |
20140080259 | MANUFACTURING METHOD FOR LAYERED CHIP PACKAGES - In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals. | 03-20-2014 |