Patent application number | Description | Published |
20140231751 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire. | 08-21-2014 |
20140252615 | SEMICONDUCTOR DEVICE USING CARBON NANOTUBE, AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring. The underlayer deactivation layer is formed on the first insulation film at a side surface of the hole, and exposes the wiring at a bottom surface of the hole. The underlayer is formed on an exposed surface of the wiring at the bottom surface of the hole and on the underlayer deactivation layer at the side surface of the hole. The catalyst layer is formed on the underlayer at the bottom surface and the side surface of the hole. The carbon nanotube extends from the catalyst layer at the bottom surface of the hole, and fills the hole. | 09-11-2014 |
20140284814 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a first wiring, a second wiring disposed in the same layer as the first wiring, a first via connected to a bottom surface of the first wiring and formed of a carbon nanotube, and a second via connected to a bottom surface of the second wiring and formed of a metal. | 09-25-2014 |
20150035149 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure. | 02-05-2015 |
20150061131 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT. | 03-05-2015 |
20150061133 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film. | 03-05-2015 |
20150111393 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND LITHOGRAPHY TEMPLATE - In the manufacturing method of a semiconductor device according to the present embodiment, a resist is supplied on a base material. A template including a first template region having a device pattern and a second template region being adjacent to the device pattern and having supporting column patterns is pressed against the resist on the base material. The resist is cured, thereby transferring the device pattern to the resist on a first material region of the base material corresponding to the first template region and at the same time transferring the supporting column patterns to the resist on a second material region of the base material corresponding to the second template region to form supporting columns. The supporting columns are contacted with the first template region when the device pattern is transferred to a resist supplied to the second material region. | 04-23-2015 |
Patent application number | Description | Published |
20100320604 | APPLICATION OF MN FOR DAMAGE RESTORATION AFTER ETCHBACK - Back end of line interconnect structures and methods of making a back end of line interconnect structure are provided. The back end of line interconnect structure contains a first interconnect layer containing a first conductive feature and a first dielectric layer; a first cap layer over the first interconnect layer, and a second interconnect layer over the first cap layer. The second interconnect layer contains a second conductive feature, a second dielectric layer, and two or more barrier layers therebetween. The two or more barrier layers contain a first barrier layer over the second dielectric layer and a MnO | 12-23-2010 |
20100323514 | RESTORATION METHOD USING METAL FOR BETTER CD CONTROLLABILITY AND CU FILING - Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/or mitigate surface erosion of the sidewall surface. As a result, the methods can improve the controllability of critical dimensions of the via and trench. | 12-23-2010 |
20110266676 | METHOD FOR FORMING INTERCONNECTION LINE AND SEMICONDUCTOR STRUCTURE - A semiconductor structure is formed by placing a thin barrier metal layer in an interconnection trench or via in a manner such that the opening of the trench or via is not obstructed by an overhang that interferes with the placement of copper into the interconnection trench or via. The material for forming a copper interconnection line contains copper and manganese. Upon annealing, a manganese oxide layer is formed having barrier properties against copper diffusion. | 11-03-2011 |
20120068347 | METHOD FOR PROCESSING SEMICONDUCTOR STRUCTURE AND DEVICE BASED ON THE SAME - Methods for fabricating a device and related device structures are provided herein. According to one embodiment, a method for fabricating a device includes the acts of producing a substrate; forming a structure on the substrate having a lower dielectric layer, a metal layer, an upper dielectric layer, a planarizing layer, and a layer of photoresist material; developing the photoresist material according to a mask pattern; etching the planarizing layer and the upper dielectric layer according to the mask pattern; removing the photoresist material and the planarizing layer upon etching of the planarizing layer and the upper dielectric layer; applying a selective metal growth or metal/organic film to respective exposed portions of the metal layer following etching of the upper dielectric layer, thereby obtaining an inverted mask pattern; and etching at least the metal layer and the lower dielectric layer according to the inverted mask pattern. | 03-22-2012 |
Patent application number | Description | Published |
20120319279 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, wiring lines formed above the semiconductor substrate, and an air gap formed between the adjacent wiring lines. In the semiconductor device, top surfaces and side walls of the wiring lines are covered with the diffusion prevention film, and the air gap is in contact with the interconnects via a diffusion prevention film. | 12-20-2012 |
20140061916 | SEMICONDUCTOR DEVICE WITH LOW RESISTANCE WIRING AND MANUFACTURING METHOD FOR THE DEVICE - According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film. | 03-06-2014 |
20140070425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires. | 03-13-2014 |
20140084250 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer. | 03-27-2014 |
20140110850 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film. | 04-24-2014 |
20150056807 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires. | 02-26-2015 |
Patent application number | Description | Published |
20100084762 | MEMORY CARD - Memory card ( | 04-08-2010 |
20100157550 | MEMORY CARD AND MEMORY CARD MANUFACTURING METHOD - A memory card includes a first circuit board, a first semiconductor chip mounted to a top face of the first circuit board with a part of its under face confronting the first circuit board, a second circuit board of which a top face is bonded to a under face of the first circuit board, a second semiconductor chip mounted to the top face of the second circuit board with at least a part of the second semiconductor chip confronting a part of another part other than the part of the under face of the first semiconductor chip, and a cover disposed over the top face of the second circuit board for covering the first semiconductor chip, the first circuit board and the second semiconductor chip. | 06-24-2010 |
20100193927 | MEMORY CARD AND METHOD FOR MANUFACTURING MEMORY CARD - A memory card includes a circuit board, a first semiconductor chip mounted on the circuit board with a bump sandwiched between the first semiconductor chip and the circuit board, a second semiconductor chip mounted on the circuit board with a bump sandwiched between the second semiconductor chip and the circuit board with a clearance not greater than 1 mm between the first semiconductor chip and the second semiconductor chip, a first sealing resin layer surrounding the bump and existing between the first semiconductor chip and the circuit board, and a second sealing resin layer surrounding the bump and existing between the second semiconductor chip and the circuit board, and a cover covering the first semiconductor chip, the second semiconductor chip on a principal face of the circuit board. | 08-05-2010 |
Patent application number | Description | Published |
20100316404 | IMAGE FORMING APPARATUS - The image forming apparatus includes a fixing portion, a temperature detection element, and a power control portion, wherein the power control portion is capable of setting a first power supply control mode for supplying power according to the detected temperature for each one control cycle, a second power supply control mode for supplying power according to the detected temperature for each one control cycle and a third power supply control mode for supplying predetermined power, and switches, immediately before a leading edge of the recording material enters the fixing portion, a state of supplying the power in the first power supply control mode to a state of supplying the power in the second power supply control mode, and then switches the state of supplying the power in the second power supply control mode to a state of supplying the power in the third power supply control mode. | 12-16-2010 |
20100322657 | FIXING APPARATUS - A fixing apparatus allows harmonic noise and flicker noise caused by alternating current to be reduced. To accomplish this, the fixing apparatus has a power supply unit that supplies AC power from a commercial power supply to a heater, a temperature detection element that detects the temperature of the heater, a setting unit that sets a duty ratio for providing power to the heater such that the temperature detected by the temperature detection element maintains a target temperature, and a control unit that controls the power supply unit such that an average power duty ratio of a single cycle equals the power duty ratio based on the detected temperature, where a single cycle is three or more full waves of the commercial power supply, there being three or more power duty ratios per one half wave of the commercial power supply in a single cycle. | 12-23-2010 |
20130209130 | IMAGE FORMING APPARATUS - The image forming apparatus includes a fixing portion, a temperature detection element, and a power control portion. The power control portion is capable of setting a first power supply control mode for supplying power according to the detected temperature for each one control cycle, a second power supply control mode for supplying power according to the detected temperature for each one control cycle and a third power supply control mode for supplying predetermined power, and switches, immediately before a leading edge of the recording material enters the fixing portion, a state of supplying the power in the first power supply control mode to a state of supplying the power in the second power supply control mode, and then switches the state of supplying the power in the second power supply control mode to a state of supplying the power in the third power supply control mode. | 08-15-2013 |
Patent application number | Description | Published |
20090103070 | Optical element and exposure apparatus - An optical element is used for an exposure apparatus which is configured to illuminate a mask with an exposure light beam for transferring a pattern on the mask onto a substrate through a projection optical system and to interpose a given liquid in a space between a surface of the substrate and the projection optical system. The optical element includes a first anti-dissolution member provided on a surface of a transmissive optical element on the substrate's side of the projection optical system. | 04-23-2009 |
20100220305 | Optical element and exposure apparatus - An optical element is used for an exposure apparatus which is configured to illuminate a mask with an exposure light beam for transferring a pattern on the mask onto a substrate through a projection optical system and to interpose a given liquid in a space between a surface of the substrate and the projection optical system. The optical element includes a first anti-dissolution member provided on a surface of a transmissive optical element on the substrate's side of the projection optical system. | 09-02-2010 |
20120206705 | OPTICAL ELEMENT AND EXPOSURE APPARATUS - An optical element is used for an exposure apparatus which is configured to illuminate a mask with an exposure light beam for transferring a pattern on the mask onto a substrate through a projection optical system and to interpose a given liquid in a space between a surface of the substrate and the projection optical system. The optical element includes a first anti-dissolution member provided on a surface of a transmissive optical element on the substrate's side of the projection optical system. | 08-16-2012 |
20120212716 | OPTICAL ELEMENT AND EXPOSURE APPARATUS - An optical element is used for an exposure apparatus which is configured to illuminate a mask with an exposure light beam for transferring a pattern on the mask onto a substrate through a projection optical system and to interpose a given liquid in a space between a surface of the substrate and the projection optical system. The optical element includes a first anti-dissolution member provided on a surface of a transmissive optical element on the substrate's side of the projection optical system. | 08-23-2012 |
20140043592 | OPTICAL ELEMENT AND EXPOSURE APPARATUS - An optical element is used for an exposure apparatus which is configured to illuminate a mask with an exposure light beam for transferring a pattern on the mask onto a substrate through a projection optical system and to interpose a given liquid in a space between a surface of the substrate and the projection optical system. The optical element includes a first anti-dissolution member provided on a surface of a transmissive optical element on the substrate's side of the projection optical system. | 02-13-2014 |
Patent application number | Description | Published |
20100028023 | OPTICAL RECEIVER - There is provided an optical receiver capable of coping with a balanced optical input, and having neither the need for adjustment of the reference voltage for single-differential conversion, nor the need for a large-capacitance capacitor corresponding to a wideband signal, for connecting the output of the trans-impedance amp to the input of the limiter amp. The optical receiver comprises a balanced photodiode composed of two units of light-sensitive elements connected in series in the direction of an identical polarity, having a bidirectional current, a differential amplifier comprising differential input pair-transistors, an emitter follower section for causing respective output signals of the differential amplifier to undergo level shift, feedback resistance for feeding back output signals of the emitter follower section to respective input terminals of the differential amplifier, and a capacitor coupled to the base of the other transistor of the differential input pair-transistors. | 02-04-2010 |
20100045387 | OPTICAL RECEIVER-AMPLIFIER - There is provided an optical receiver-amplifier wherein the need for a large capacitance capacitor for AC coupling is eliminated to thereby enable miniaturization of a receiver in whole, and output waveforms of a differential limiter amp can be rendered symmetrical with high precision while a transimpedance amp and a limiter amp can be integrated on one chip. The optical receiver-amplifier comprises a photodiode, a transimpedance amp for amplifying an output signal of the photodiode, and a DC current compensating circuit connected in parallel with the transimpedance amp for compensating for a DC-current component of an output current of the differential amp. | 02-25-2010 |