Patent application number | Description | Published |
20130070606 | INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE - Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices. | 03-21-2013 |
20130170525 | WIRE LIKE LINK FOR CYCLE REPRODUCIBLE AND CYCLE ACCURATE HARDWARE ACCELERATOR - First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency. | 07-04-2013 |
20130318107 | GENERATING DATA FEED SPECIFIC PARSER CIRCUITS - Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated. | 11-28-2013 |
20140032509 | ACCELERATED ROW DECOMPRESSION - A method comprises streaming one or more pages of a database to a hardware accelerator, extracting one or more rows from each of the one or more pages of the database, determining whether a given one of the extracted rows is compressed, decompressing the given one of the extracted rows responsive to the determination and outputting the decompressed row. The decompressing step is performed in the hardware accelerator. The hardware accelerator may be a field-programmable gate array. The method allows for hardware accelerated row decompression. | 01-30-2014 |
20140032516 | ACCELERATED ROW DECOMPRESSION - An apparatus comprises a hardware accelerator coupled to a memory. The hardware accelerator comprises one or more decompression units. The one or more decompression units are reconfigurable. The hardware accelerator may be a field-programmable gate array. The hardware accelerator may also comprise one or more reconfigurable scanner units. The one or more decompression units, in the aggregate, are operative to decompress one or more rows of a database at a bus speed of the coupling between the hardware accelerator and the memory. Two or more decompression units are operative to decompress two or more rows of a database in parallel. The apparatus allows for hardware accelerated row decompression. | 01-30-2014 |
20140067845 | FACILITATING FIELD PROGRAMMABLE GATE ARRAY ACCELERATIONS OF DATABASE FUNCTIONS - Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array. | 03-06-2014 |
20140067851 | FACILITATING FIELD PROGRAMMABLE GATE ARRAY ACCELERATIONS OF DATABASE FUNCTIONS - Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array. | 03-06-2014 |
Patent application number | Description | Published |
20080215854 | System and Method for Adaptive Run-Time Reconfiguration for a Reconfigurable Instruction Set Co-Processor Architecture - A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed. | 09-04-2008 |
20120117413 | METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) - A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided. | 05-10-2012 |
20130318067 | HARDWARE-ACCELERATED RELATIONAL JOINS - Techniques are provided for hardware-accelerated relational joins. A first table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the first table is hashed to set at least one bit in at least one bit vector. A second table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the second table is hashed to generate at least one hash value. At least one bit vector is probed using the at least one hash value. A joined row is constructed responsive to the probing step. The row-construction step is performed in the hardware accelerator. | 11-28-2013 |
20140188908 | RADIX SORT WITH READ-ONLY KEY - Methods and arrangements for a radix sort with a read only key. A plurality of keys are received, an array and a link table are populated for the first digit of the keys based upon the keys; and an array and a link table are populated for each successive digit of the keys based upon the array and link table populated for the preceding digit of the keys. Embodiments may be implemented in both hardware (FPGAs, ASICs, information handling devices, etc.) and software. Other embodiments are also disclosed and claimed. | 07-03-2014 |
20140188909 | RADIX SORT WITH READ-ONLY KEY - Methods and arrangements for a radix sort with a read only key. A plurality of keys are received, an array and a link table are populated for the first digit of the keys based upon the keys; and an array and a link table are populated for each successive digit of the keys based upon the array and link table populated for the preceding digit of the keys. Embodiments may be implemented in both hardware (FPGAs, ASICs, information handling devices, etc.) and software. Other embodiments are also disclosed and claimed. | 07-03-2014 |
20150026220 | OFFLOADING PROJECTION OF FIXED AND VARIABLE LENGTH DATABASE COLUMNS - In an exemplary embodiment of this disclosure, a computer-implemented method includes determining that a database query warrants a first projection operation to project a plurality of input rows to a plurality of projected rows, where each of the plurality of input rows has one or more variable-length columns. A first projection control block is constructed, by a computer processor, to describe the first projection operation. The first projection operation is offloaded to a hardware accelerator. The first projection control block is provided to the hardware accelerator, and the first projection control block enables the hardware accelerator to perform the first projection operation at streaming rate. | 01-22-2015 |
20150046427 | ACCELERATING MULTIPLE QUERY PROCESSING OPERATIONS - Embodiments include methods, systems and computer program products a for offloading multiple processing operations to an accelerator includes receiving, by a processing device, a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator. | 02-12-2015 |
20150046428 | SCALABLE ACCELERATION OF DATABASE QUERY OPERATIONS - Embodiments include methods, systems and computer program products for offloading multiple processing operations to an accelerator. Aspects include receiving a database query from an application, performing an analysis on the query, and identifying a plurality of available accelerators. Aspects further include retrieving cost information for one or more templates available on each of the plurality of available accelerators, determining a query execution plan based on the cost information and the analysis on the query, and offloading one or more query operations to at least one of the plurality of accelerators based on the query execution plan. | 02-12-2015 |
20150046430 | SCALABLE ACCELERATION OF DATABASE QUERY OPERATIONS - Embodiments include methods, systems and computer program products for offloading multiple processing operations to an accelerator. Aspects include receiving a database query from an application, performing an analysis on the query, and identifying a plurality of available accelerators. Aspects further include retrieving cost information for one or more templates available on each of the plurality of available accelerators, determining a query execution plan based on the cost information and the analysis on the query, and offloading one or more query operations to at least one of the plurality of accelerators based on the query execution plan. | 02-12-2015 |
20150046453 | TUNABLE HARDWARE SORT ENGINE FOR PERFORMING COMPOSITE SORTING ALGORITHMS - Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys. | 02-12-2015 |
20150046475 | HARDWARE IMPLEMENTATION OF A TOURNAMENT TREE SORT ALGORITHM - Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator. The method includes receiving a plurality of key values by the hardware accelerator, storing each the plurality of keys into a location on a memory of the hardware accelerator, and creating a pointer to each of the locations of the plurality of keys. The method also includes storing the pointer to each of the plurality of keys into a first array stored by the hardware accelerator, sorting the plurality of keys by ordering the pointers in the first array and by using a second array for storing the pointers, wherein the sorting identifies a winning key from the plurality of keys in the memory, and outputting the winning key. | 02-12-2015 |
20150046476 | TUNABLE HARDWARE SORT ENGINE FOR PERFORMING COMPOSITE SORTING ALGORITHMS - Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys. | 02-12-2015 |
20150046478 | HARDWARE IMPLEMENTATION OF A TOURNAMENT TREE SORT ALGORITHM - Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator. The method includes receiving a plurality of key values by the hardware accelerator, storing each the plurality of keys into a location on a memory of the hardware accelerator, and creating a pointer to each of the locations of the plurality of keys. The method also includes storing the pointer to each of the plurality of keys into a first array stored by the hardware accelerator, sorting the plurality of keys by ordering the pointers in the first array and by using a second array for storing the pointers, wherein the sorting identifies a winning key from the plurality of keys in the memory, and outputting the winning key. | 02-12-2015 |
20150046486 | ACCELERATING MULTIPLE QUERY PROCESSING OPERATIONS - Embodiments include methods, systems and computer program products a for offloading multiple processing operations to an accelerator includes receiving, by a processing device, a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator. | 02-12-2015 |
Patent application number | Description | Published |
20110264218 | INTERVERTEBRAL BODY IMPLANT, INSTRUMENT AND METHOD - Interbody implant systems and methods of implant interbody implants are described. In one aspect, an implant includes a body have a distal end portion and a proximal end portion and a first articulation surface formed at a distal end of the distal end portion. An insertion instrument includes an elongate shaft having a proximal end portion and a distal end portion; and a second articulation surface formed at a distal end of the distal end portion. The second articulation surface is configured to interface with the first articulation surface. An attachment member is configured to connect the implant to the insertion instrument. The attachment member is actuatable to compress the first and second articulation surfaces together in a locked configuration with sufficient force to prevent relative rotation between the first and second articulation surfaces. The attachment member is actuatable to reduce an amount of compression force existing in the locked configuration to place the first and second articulation surfaces in an unlocked configuration such that the first articulation surface can rotate relative to the second articulation surface. | 10-27-2011 |
20110301710 | INTERVERTEBRAL IMPLANT FACILITATING UNILATERAL PLACEMENT, INSTRUMENTS AND METHODS - Implants, tools and methods for performing unilateral posterior lumbar interbody fusion are provided. An interbody implant includes a body having a top and bottom surface extending along a length thereof; and first and second side surfaces extending between the top and bottom surfaces on opposite sides of the body. The height of the first side surface is greater than the height of the second side surface. | 12-08-2011 |
20120179207 | SURGICAL PLATE SYSTEM AND METHOD - A surgical plate system, components and methods of using are described. A surgical plate system includes a plate having an anterior surface, a posterior surface, a longitudinal axis, a transverse axis and a through hole passing through the anterior and posterior surfaces. A variable fastener is configured and dimensioned to connect to the plate, the variable fastener having a head and a shaft extending distally from the head. The head is configured to assume different proximal end diameters. The head, in a first configuration allows inward flexing to reduce a diameter of the head to allow the head to pass through an entrance opening of the through hole. In a second configuration, the head is prevented from flexing inwardly thereby preventing the head from backing out of the entrance opening, while allowing articulation of the head, within the through hole, relative to the plate. | 07-12-2012 |
20120245641 | Devices, Systems and Methods of Attaching Same to the Spine - Systems and method for fixation to a spinal column are described. A system includes a plate having an anterior surface, a posterior surface, a longitudinal axis, a transverse axis and a through hole passing through the anterior and posterior surfaces; and a dynamic fixator interface member configured and dimensioned to connect to the plate within the through hole and to axially slide relative to the plate in directions of the longitudinal axis, and additionally, to rotate relative to the plate in directions about the transverse axis. | 09-27-2012 |
20120265311 | Intervertebral Implant Facilitating Unilateral Placement, Instruments and Methods - Implants, tools and methods for performing unilateral posterior lumbar interbody fusion are provided. An interbody implant includes a body having a top and bottom surface extending along a length thereof; and first and second side surfaces extending between the top and bottom surfaces on opposite sides of the body. The height of the first side surface is greater than the height of the second side surface. | 10-18-2012 |
20140046372 | Systems, Assemblies and Methods for Spinal Derotation - Systems, assemblies, components and methods for correcting alignment of one or more vertebrae of a spine are provided. A first elongate derotator member includes a first elongate element having a first proximal end portion and a first distal end portion. The first distal end portion is releasably engageable with a first implant implanted in one of the vertebrae. A second elongate derotator member comprising a second elongate element is releasably engageable with a second implant implanted in the same vertebra. A transverse member is engageable with the first and second elongate elements. A first channel extends axially through the first elongate element and a second channel extends axially through the second elongate element such that a proximal end portion of the first implant can be accessed from a proximal end portion of the first elongate element by inserting a tool through the first channel and a proximal end portion of the second implant can be accessed from a proximal end portion of the second elongate element by inserting the tool or another tool through the second channel. | 02-13-2014 |
20140046374 | Staged Locking of Surgical Screw Assembly - A surgical screw assembly including: a fastener including an elongate shaft having a proximal end and a distal end and a head at the proximal end. A tulip having a an internal bearing surface is provided. A distal end of the tulip has a bore therethrough defining the internal bearing surface. Locking enhancement features are configured to cooperate with the head, such that, in an unlocked configuration, the head is movable relative to the tulip; in a provisionally locked configuration, the locking enhancement features engage the head with a first polyaxial grip strength; and in a finally locked configuration, the locking enhancement features engage the head with a second polyaxial grip strength greater than the first polyaxial grip strength. | 02-13-2014 |
20140046385 | Locking Force Augmentation Features for Surgical Screw Assembly - A surgical screw assembly is provided that includes a fastener including an elongate shaft having a proximal end and a distal end and a head at the proximal end. A tulip having an internal bearing surface and a distal end having a bore therethrough is provided to allow the distal end of the elongate shaft to pass therethrough. A first step feature located at a distal end portion of the bore and extending inwardly therefrom reduces the diameter of the bore to allow the distal end of the elongate shaft to pass therethrough, but prevents passage of the head therethrough. A second step feature located at a distal end portion of the bore, distally of the first step feature, further reduces the diameter of the bore to a dimension less than a dimension established by the first step feature, the further reduced dimension allowing the distal end of the elongate shaft to pass therethrough, but preventing passage of the head therethrough. | 02-13-2014 |
20140046386 | Uniplanar Surgical Screw Assembly - Uniplanar surgical screw assemblies described include: a fastener including an elongate shaft; a saddle-shaped tulip having a tulip having a bore therethrough dimensioned to allow the distal end of the elongate shaft to pass therethrough, but to prevent passage of the head therethrough; and one or more features for limiting angular movement of the shaft, relative to the tulip, to one plane. | 02-13-2014 |
20150066148 | Intervertebral Implant Facilitating Unilateral Placement, Instruments and Methods - Implants, tools and methods for performing unilateral posterior lumbar interbody fusion are provided. An interbody implant includes a body having a top and bottom surface extending along a length thereof; and first and second side surfaces extending between the top and bottom surfaces on opposite sides of the body. The height of the first side surface is greater than the height of the second side surface. | 03-05-2015 |
20150119990 | Intervertebral Body Implant, Instrument and Method - Interbody implant systems and methods of implant interbody implants are described. In one aspect, an implant includes a body have a distal end portion and a proximal end portion and a first articulation surface formed at a proximal end of the proximal end portion. An insertion instrument includes an elongate shaft having a proximal end portion and a distal end portion; and a second articulation surface formed at a distal end of the distal end portion. The second articulation surface is configured to interface with the first articulation surface. An attachment member is configured to connect the implant to the insertion instrument. The attachment member is actuatable to compress the first and second articulation surfaces together in a locked configuration with sufficient force to prevent relative rotation between the first and second articulation surfaces. The attachment member is actuatable to reduce an amount of compression force existing in the locked configuration to place the first and second articulation surfaces in an unlocked configuration such that the first articulation surface can rotate relative to the second articulation surface. | 04-30-2015 |