Patent application number | Description | Published |
20100308418 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor. | 12-09-2010 |
20110170337 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor. | 07-14-2011 |
20130292769 | Transistor With Reduced Charge Carrier Mobility And Associated Methods - One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type. | 11-07-2013 |
Patent application number | Description | Published |
20080283925 | Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement - In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another. | 11-20-2008 |
20120223396 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. | 09-06-2012 |
20120224415 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter. | 09-06-2012 |
20140002161 | CIRCUIT ARRANGEMENT, A RETENTION FLIP-FLOP, AND METHODS FOR OPERATING A CIRCUIT ARRANGEMENT AND A RETENTION FLIP-FLOP | 01-02-2014 |
20140003136 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS | 01-02-2014 |