Patent application number | Description | Published |
20090044086 | Error correction in a set associative storage device - A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access. | 02-12-2009 |
20090164727 | Handling of hard errors in a cache of a data processing apparatus - A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. The cache storage comprising data storage having a plurality of cache lines for storing data values, and address storage having a plurality of entries, with each entry identifying for an associated cache line an address indication value, and each entry having associated error data. In response to an access request, a lookup procedure is performed to determine with reference to the address indication value held in at least one entry of the address storage whether a hit condition exists in one of the cache lines. Further, error detection circuitry determines with reference to the error data associated with the at least one entry of the address storage whether an error condition exists for that entry. Additionally, cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of the error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. Further, the error detection circuitry causes a clean and invalidate operation to be performed in respect of the specific cache line, and the access request is then re-performed. The cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from the lookup procedure. This mechanism provides a very simple and effective mechanism for handling hard errors that manifest themselves within a cache during use, so as to ensure correct operation of the cache in the presence of such hard errors. Further, the technique can be employed not only in association with write through caches but also write back caches, thus providing a very flexible solution. | 06-25-2009 |
20090164870 | Apparatus and method for error correction of data values in a storage device - A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects if an error is present in that data value and, if necessary, error correction circuitry corrects the read data value. An error cache having at least one entry stores corrected replacement data values, a corrected data value being allocated into an entry of the error cache for every corrected data value that is generated, and the read access request is re-performed. Replacement data values are read from the error cache in preference to data values stored in the storage device. This ensures that the retry mechanism will succeed irrespective of whether the error was a soft error or a hard error. Thus, if any hard errors do occur during normal operation of the storage device, they can effectively be temporarily corrected through use of the error cache to ensure that the retry mechanism proceeds correctly. | 06-25-2009 |
20110040815 | Apparatus and method for performing fused multiply add floating point operation - A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus | 02-17-2011 |
20110093686 | Register state saving and restoring - In a data processing apparatus | 04-21-2011 |
20110103400 | Check data encoding using parallel lane encoders - An encoder for generating check data to accompaning payload data uses parallel lane encoders | 05-05-2011 |
20110173482 | Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations - A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults. | 07-14-2011 |
20110179255 | Data processing reset operations - A processor | 07-21-2011 |
20110179308 | Auxiliary circuit structure in a split-lock dual processor system - A multiple-processor system | 07-21-2011 |
20110179309 | Debugging a multiprocessor system that switches between a locked mode and a split mode - A data processing system | 07-21-2011 |
20110191543 | Area and power efficient data coherency maintenance - An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device. | 08-04-2011 |
20110264827 | Performance by reducing transaction request ordering requirements - A data processing apparatus is disclosed that is configured to communicate via an output port with a plurality of devices and to issue a stream of transaction requests to the output port, the stream of transaction requests comprising at least some device transaction requests destined for the plurality of devices. Device transactions are transactions that may affect each other and therefore should be completed in an order in which they are received at the output port in. The output port is configured to output the received transaction requests as a single serial stream of transaction requests. The data processing apparatus comprises: a destination device detector for monitoring the device transaction requests and for determining which of the plurality of devices each of the device transaction requests are destined for; the output port comprises ordering circuitry configured to treat the plurality of devices as at least two subsets of devices, at least one of the subsets comprising at least two devices; the ordering circuitry being configured to receive the stream of transaction requests and to classify each of the device transaction requests into one of the at least two subsets in response to determination of a destination device by said destination device detector, and to maintain said order that said device transaction requests within each subset are received in, such that device transaction requests within each subset are output by the output port and executed by their respective destination devices in the received order, while device transaction requests within different subsets may be output in an order that is different to the received order. | 10-27-2011 |
20120260070 | THREAD SELECTION FOR MULTITHREADED PROCESSING - A multithreading processor | 10-11-2012 |