Patent application number | Description | Published |
20140003117 | PINNING MAGNETIC DOMAIN WALLS IN A MAGNETIC DOMAIN SHIFT REGISTER MEMORY DEVICE | 01-02-2014 |
20140003118 | MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES | 01-02-2014 |
20140003119 | PINNING MAGNETIC DOMAIN WALLS IN A MAGNETIC DOMAIN SHIFT REGISTER MEMORY DEVICE | 01-02-2014 |
20140004625 | MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES | 01-02-2014 |
20140126280 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 05-08-2014 |
20140126281 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 05-08-2014 |
20140127830 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A method of forming a magnetoresistive random access memory (MRAM) apparatus includes forming a first conductive line on a first insulating layer, forming a second insulating layer on the first conductive line and forming a magnetic tunnel junction through the second insulating layer to contact the first conductive line. The method also includes forming a cavity adjacent to the magnetic tunnel junction in the second insulating layer and forming a second conductive line on the second insulating layer to contact the magnetic tunnel junction. | 05-08-2014 |
20140160829 | METHOD AND APPARATUS FOR CONTROLLED APPLICATION OF OERSTED FIELD TO MAGNETIC MEMORY STRUCTURE - An apparatus for applying Oersted fields to a magnetic memory device comprises a first metal layer; a first insulating layer positioned on the first metal layer; a magnetic shift register wire positioned on the first insulating layer; a second insulating layer positioned on the magnetic shift register wire; a second metal layer positioned on the second insulating layer; a first conducting wire positioned in the first metal layer and extending transverse to the magnetic shift register wire; and a second conducting wire positioned in the second metal layer and extending transverse to the magnetic shift register wire. The first conducting wire is offset relative to the second conducting wire, the offset being defined by a distance between a first axis normal to the magnetic shift register wire and through the first conducting wire and a second axis normal to the magnetic shift register wire and through the second conducting wire. | 06-12-2014 |
20140204647 | RACETRACK MEMORY CELLS WITH A VERTICAL NANOWIRE STORAGE ELEMENT - A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire. | 07-24-2014 |
20140204648 | RACETRACK MEMORY CELLS WITH A VERTICAL NANOWIRE STORAGE ELEMENT - A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire. | 07-24-2014 |
20140264666 | CELL DESIGN FOR EMBEDDED THERMALLY-ASSISTED MRAM - A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap. | 09-18-2014 |
20140264670 | CELL DESIGN FOR EMBEDDED THERMALLY-ASSISTED MRAM - A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap. | 09-18-2014 |
20140268981 | RACETRACK MEMORY WITH ELECTRIC-FIELD ASSISTED DOMAIN WALL INJECTION FOR LOW-POWER WRITE OPERATION - Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire. | 09-18-2014 |
20140268982 | RACETRACK MEMORY WITH ELECTRIC-FIELD ASSISTED DOMAIN WALL INJECTION FOR LOW-POWER WRITE OPERATION - Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire. | 09-18-2014 |
20140268987 | Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization - A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer. | 09-18-2014 |
20140269028 | Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization - A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer. | 09-18-2014 |
20140273284 | THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY - A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). The device includes a magnetic tunnel junction configured to store data, a first multilayer contact structure positioned on one end of the magnetic tunnel junction, and a second multilayer contact structure positioned on an opposite end of the magnetic tunnel junction. The first multilayer contact structure and the second multilayer contact structure each include multiple layers of metals. The multiple layers of metals are structured to inhibit thermal conductivity between the magnetic tunnel junction and surrounding structures, and the multiple layers of metals are structured to electrically conduct electrical current. | 09-18-2014 |
20140353782 | THERMALLY ASSISTED MRAM WITH A MULTILAYER ENCAPSULANT FOR LOW THERMAL CONDUCTIVITY - A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction. | 12-04-2014 |
20140356979 | THERMALLY ASSISTED MRAM WITH A MULTILAYER ENCAPSULANT FOR LOW THERMAL CONDUCTIVITY - A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction. | 12-04-2014 |