Patent application number | Description | Published |
20110240859 | ALTERNATIVE PIXEL SHAPE FOR UNCOOLED MICRO-BOLOMETER - An infrared imaging system including a substrate, a plurality of hexagonal shaped micro-bolometer pixels combined to define a focal plane array. Each pixel is electrically connected to the substrate with a pair of opposing isolation legs. One end of the isolation leg is attached to the pixel's periphery while the other is fixed to that substrate so that the focal plane array and a plane containing the substrate have a parallel, spaced-apart relationship. In this manner, the isolation legs provides an electrical communication path from each pixel to the substrate as each pixel undergoes an internal change in resistance due to absorption of infrared energy. At the same time, the legs separate the pixels from the substrate so that there is no heat transfer between the pixel and the substrate due to direct contact. The hexagonal shape arrangement also allows for a staggered arrangement of adjacent rows in the array, thereby increasing the fill factor for the focal plane array of the device. The addition of stepped areas to the hexagonal pixel provides for improved energy absorption through increase in area and multiple coupling of resonant cavities between the pixel and the substrate. | 10-06-2011 |
20130016270 | Radial Readout Approach to EO ImagersAANM Antesberger; A. WayneAACI WoodbridgeAAST VAAACO USAAGP Antesberger; A. Wayne Woodbridge VA US - A radial based approach to electro-optic imagers, rather than the conventional rectilinear approach, would have basic overall system design advantages. Those system design advantages would apply to the components and the entire system implementation and include approaches to objective optical design, focal plane array FPA with fill factor, FPA layout and associated read-out integrated circuit ROIC, support electronics architecture and associated memory requirements, image processing IP algorithms, display layout and format, and eyepiece optics. A radial based approach to EO imagers would yield a device/system with attributes requiring less complicated optical components, with potentially fewer elements, for both the objective and eyepiece lenses. In addition, alternative objective optics could be more easily employed, such as holographic or wave front coded, due to reduced complexity of implementing correction algorithms as a result of referencing the system around its optical axis. The radial readout EO system would have pixel ‘one’ at the center and be ‘read out and displayed’ like the rings of a tree rather than words on a page. | 01-17-2013 |
Patent application number | Description | Published |
20110126408 | Method of making high density interposer and electronic package utilizing same - A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings. | 06-02-2011 |
20110127664 | Electronic package including high density interposer and circuitized substrate assembly utilizing same - An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided. | 06-02-2011 |
20110284273 | POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME - A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core. | 11-24-2011 |
20120031649 | CORELESS LAYER BUILDUP STRUCTURE WITH LGA AND JOINING LAYER - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging. | 02-09-2012 |
20120160544 | CORELESS LAYER BUILDUP STRUCTURE WITH LGA - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging. | 06-28-2012 |
20120160547 | CORELESS LAYER BUILDUP STRUCTURE - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. | 06-28-2012 |
20130025839 | THERMAL SUBSTRATE - An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure. | 01-31-2013 |