| Patent application number | Description | Published |
|---|
| 20150093863 | METHOD OF MAKING A FLOATING GATE NON-VOLATILE MEMORY (NVM) WITH BREAKDOWN PREVENTION - A method of making a semiconductor structure includes patterning a polysilicon layer on a substrate to form a first floating gate over a first active region in the substrate and a second floating gate over a second active region in the substrate. An opening between the first and second floating gates is filled with a dielectric material. The dielectric material is etched back so that a height of a remaining portion of the dielectric material is less than a height of the first and second floating gates. A second polysilicon layer is deposited over the first and second floating gates and the remaining portion of the dielectric material to form a word line for the first and second floating gates. | 04-02-2015 |
| 20150214062 | Methods For Extending Floating Gates For NVM Cells To Form Sub-Lithographic Features And Related NVM Cells - Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability. | 07-30-2015 |
| 20150249091 | NVM LAYOUT - A memory device can include an array of NOR memory cells, each memory cell including a floating gate, a source on a source side of the floating gate, a drain on a drain side of the floating gate, a drain contact on the drain, and a source contact on the source. The source contacts are connected to a common source line. A plurality of bit lines are connected to respective drains in a column of the memory cells. A plurality of word lines, each word line coupled to respective floating gates in a row of the memory cells. Spacing between the word lines on the drain side is greater than spacing between the word lines on the source side. | 09-03-2015 |
| 20150364478 | METHODS AND STRUCTURES FOR SPLIT GATE MEMORY CELL SCALING WITH MERGED CONTROL GATES - A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate. | 12-17-2015 |
| 20150371711 | CONTROL GATE DRIVER FOR USE WITH SPLIT GATE MEMORY CELLS - A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate. | 12-24-2015 |
| 20160019964 | MEMORY DEVICE WITH COMBINED NON-VOLATILE MEMORY (NVM) AND VOLATILE MEMORY - A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode. | 01-21-2016 |
| 20160064092 | FLASH MEMORY WITH IMPROVED READ PERFORMANCE - A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells. | 03-03-2016 |
| 20160087057 | Low Resistance Polysilicon Strap - A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region. | 03-24-2016 |
| 20160093671 | NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) - A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line. | 03-31-2016 |
