Patent application number | Description | Published |
20100091548 | Non-Volatile Memory Array with Resistive Sense Element Block Erase and Uni-Directional Write - A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device. | 04-15-2010 |
20100097841 | Multi-Stage Parallel Data Transfer - Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step. | 04-22-2010 |
20100118589 | Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device - A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs. | 05-13-2010 |
20100118590 | Bidirectional Non-Volatile Memory Array Architecture - A bidirectional memory array architecture for non-volatile memory is disclosed. In accordance with some embodiments, a plurality of memory cells are arranged into an M number of rows and an N number of columns with each memory cell having a resistive sense element (RSE) and a switching device. A total number of M+N+1 control lines extend adjacent to and are connected with the memory cells to facilitate bi-directional programming of resistive states to each memory cell. | 05-13-2010 |
20100118602 | DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF - A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line. | 05-13-2010 |
20110007550 | Current Magnitude Compensation for Memory Cells in a Data Storage Array - A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines. | 01-13-2011 |
20110007581 | Current Cancellation for Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current. | 01-13-2011 |
20110026305 | Non-Volatile Memory Array With Resistive Sense Element Block Erase and Uni-Directional Write - A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device. | 02-03-2011 |
20110149639 | Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device - A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs. | 06-23-2011 |
20110182106 | Current Cancellation for Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current. | 07-28-2011 |
20120147659 | Bidirectional Non-Volatile Memory Array Architecture - Method and apparatus for transferring data in a memory. A semiconductor memory includes a plurality of memory cells each having a resistive sense element (RSE) in series with a switching device. A conductive word line extends in a first direction adjacent the memory cells and is connected to a gate structure of each of the switching devices. A plurality of conductive bit lines extend in a second direction adjacent the memory cells, each bit line providing a connection node that interconnects a respective pair of the memory cells. A control circuit senses a programmed state of a selected memory cell by setting each of the bit lines on a first side of the selected memory cell to a first voltage level, setting each of the remaining bit lines on an opposing second side of the selected memory cell to a second voltage level, and setting the word line to a third voltage level. | 06-14-2012 |