Patent application number | Description | Published |
20100128813 | Multi-channel Signaling with Equalization - A data transmission circuit comprises a plurality of data preparation circuits and a combiner. Each data preparation circuit receives a respective data stream and generates a respective sub-channel signal. Each respective data stream has a respective symbol rate and a respective Nyquist bandwidth. The combiner combines the respective sub-channel signals to generate a data transmission signal having an associated bandwidth. The bandwidth associated with the data transmission signal is greater than or equal to the sum of the Nyquist bandwidths for the respective data streams. Each data preparation circuit comprises a programmable linear equalizer that equalizes the respective sub-channel signal across the bandwidth of the data transmission signal. | 05-27-2010 |
20110019722 | Per-Tone Delay Adjustment for Multi-Tone Systems - A data transmission circuit has an interface for receiving a data stream for transmission, a data stream splitter, a plurality of parallel data preparation circuits, and a combiner. The data stream splitter splits the data stream to produce multiple substreams, the plurality of parallel data preparation circuits prepare a respective substream for transmission and generate a respective sub-channel signal, and the combiner combines the respective sub-channel signals to generate a data transmission signal. At least two of the plurality of data preparation circuits each include a programmable element for delaying the corresponding substream. | 01-27-2011 |
20110228864 | RESONANCE MITIGATION FOR HIGH-SPEED SIGNALING - The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link. | 09-22-2011 |
20120139638 | Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and Temperature - A receiver includes an amplifier and a transconductance bias circuit. The amplifier gain is largely determined by transconductance and load impedance. The transconductance bias circuit varies the transconductance in inverse proportion to the load impedance to maintain the gain over process, voltage, and temperature. Differential amplifiers can use separate transconductance bias circuits for each amplifier leg, and the bias circuits can be independently controlled to minimize common-mode gain and voltage offsets. | 06-07-2012 |
20120147944 | HIGH RESOLUTION OUTPUT DRIVER - High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions. | 06-14-2012 |
20120187978 | Methods and Circuits for Calibrating Multi-Modal Termination Schemes - Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area. | 07-26-2012 |
20130051162 | CODED DIFFERENTIAL INTERSYMBOL INTERFERENCE REDUCTION - Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links. | 02-28-2013 |
20130063191 | Methods and Circuits for Duty-Cycle Correction - A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle. | 03-14-2013 |
20130114363 | MULTI-MODAL MEMORY INTERFACE - A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques. | 05-09-2013 |
20130194881 | AREA-EFFICIENT MULTI-MODAL SIGNALING INTERFACE - One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus enabling those pins to be used as C/A pins when the PHY is connected to some memory types, and as DQ pins when the PHY is connected to other memory types. | 08-01-2013 |
20130278296 | Multi-Modal Communication Interface - An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage. | 10-24-2013 |
20130342240 | PARTIAL RESPONSE DECISION FEEDBACK EQUALIZER WITH SELECTION CIRCUITRY HAVING HOLD STATE - A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence. | 12-26-2013 |
20140023161 | CROSSTALK REDUCTION CODING SCHEMES - Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link. | 01-23-2014 |
20140101382 | DATA BUFFER WITH A STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE - A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface. | 04-10-2014 |
20140104935 | SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING - A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams. | 04-17-2014 |
20140210545 | ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATION - An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current. | 07-31-2014 |
20140237152 | Folded Memory Modules - A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module. | 08-21-2014 |
20140314171 | MISMATCHED DIFFERENTIAL CIRCUIT - A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator. | 10-23-2014 |
20140314173 | PVT TOLERANT DIFFERENTIAL CIRCUIT - An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver. | 10-23-2014 |
20140347092 | MODULATED ON-DIE TERMINATION - Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest. | 11-27-2014 |
20150016580 | POINT TO MULTI-POINT CLOCK-FORWARDED SIGNALING FOR LARGE DISPLAYS - A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter. | 01-15-2015 |
Patent application number | Description | Published |
20080297213 | Signaling with Superimposed Clock and Data Signals - A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal. | 12-04-2008 |
20080310491 | MULTI-MODE TRANSMITTER - A multi-mode transmitter within an integrated circuit device. The multi-mode transmitter transmits a first data sequence in a baseband signal when a first transmission mode is enabled, and transmits the first data sequence in a multi-band signal when a second transmission mode is enabled. | 12-18-2008 |
20090067537 | Adjustable Dual-Band Link - A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a baseband sub-channel and the passband circuit corresponds to a passband sub-channel. The first communication link circuit also includes a circuit that distributes a first subset of a data stream having a first symbol rate to the baseband circuit and a second subset of the data stream having a second symbol rate to the passband circuit. The baseband sub-channel and the passband sub-channel are separated by an adjacent guardband of frequencies. The passband carrier frequency is adjusted to define the guardband and the guardband corresponds to a first notch in a channel response of a first communications channel. | 03-12-2009 |
20100020898 | Adjustable Dual-Band Link - A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a baseband sub-channel and the passband circuit corresponds to a passband sub-channel. The first communication link circuit also includes a circuit that distributes a first subset of a data stream having a first symbol rate to the baseband circuit and a second subset of the data stream having a second symbol rate to the passband circuit. The baseband sub-channel and the passband sub-channel are separated by an adjacent guardband of frequencies. The passband carrier frequency is adjusted to define the guardband and the guardband corresponds to a first notch in a channel response of a first communications channel. | 01-28-2010 |
20110150051 | Multi-Tone System with Oversampled Precoders - A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal. | 06-23-2011 |
20110184999 | Linear Transformation Circuit - A first device includes a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit as an input to receive a vector having N digital values and an output to output N first output signals. The linear transformation circuit optionally includes a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H. The linear transformation circuit includes a digital-to-analog conversion (DAC) circuit coupled to the output of the sign-adjustment circuit. Outputs from the DAC circuit are summed to produce an output. | 07-28-2011 |
20120189045 | Signaling with Superimposed Clock and Data Signals - A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal. | 07-26-2012 |