Patent application number | Description | Published |
20080237590 | DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR - A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. | 10-02-2008 |
20080237797 | ELECTRICALLY TUNABLE RESISTOR AND RELATED METHODS - An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor. | 10-02-2008 |
20080297188 | IC CHIP STRESS TESTING - Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current I | 12-04-2008 |
20090121259 | PAIRED MAGNETIC TUNNEL JUNCTION TO A SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor. | 05-14-2009 |
20090251167 | Array-Based Early Threshold Voltage Recovery Characterization Measurement - A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed. | 10-08-2009 |
20100200953 | ON-CHIP HEATER AND METHODS FOR FABRICATION THEREOF AND USE THEREOF - An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure. | 08-12-2010 |
20100258900 | ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures. | 10-14-2010 |
20100318313 | MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES - System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms. | 12-16-2010 |
20100327892 | Parallel Array Architecture for Constant Current Electro-Migration Stress Testing - A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic. | 12-30-2010 |
20120015511 | ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures. | 01-19-2012 |