Patent application number | Description | Published |
20090043527 | COMPUTER-IMPLEMENTED METHODS, CARRIER MEDIA, AND SYSTEMS FOR GENERATING A METROLOGY SAMPLING PLAN - Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology. | 02-12-2009 |
20090055783 | COMPUTER-IMPLEMENTED METHODS FOR DETERMINING IF ACTUAL DEFECTS ARE POTENTIALLY SYSTEMATIC DEFECTS OR POTENTIALLY RANDOM DEFECTS - Various computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects are provided. One computer-implemented method for determining if actual defects are potentially systematic defects or potentially random defects includes comparing a number of actual defects in a group to a number of randomly generated defects in a group. The actual defects are detected on a wafer. A portion of a design on the wafer proximate a location of each of the actual defects in the group and each of the randomly generated defects in the group is substantially the same. The method also includes determining if the actual defects in the group are potentially systematic defects or potentially random defects based on results of the comparing step. | 02-26-2009 |
20090297019 | METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA - Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium. | 12-03-2009 |
20110170091 | INSPECTION GUIDED OVERLAY METROLOGY - Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations. | 07-14-2011 |
20110172804 | Scanner Performance Comparison And Matching Using Design And Defect Data - A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively. | 07-14-2011 |
20120141013 | REGION BASED VIRTUAL FOURIER FILTER - The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima. | 06-07-2012 |
20120216169 | DESIGN BASED DEVICE RISK ASSESSMENT - The present invention includes defining a multiple patterns of interest utilizing design data of the device; generating a design based classification database, the DBC database including design data associated with each of the POIs; receiving one or more inspection results; comparing the inspection results to each of the plurality of POIs in order to identify an occurrence of at least one of the POIs in the inspection results; determining yield impact of each POI utilizing process yield data; monitoring a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device; and determining a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons, the critical polygons defined utilizing design data of the device. | 08-23-2012 |
20120316855 | Using Three-Dimensional Representations for Defect-Related Applications - Various embodiments for using three-dimensional representations for defect-related applications are provided. | 12-13-2012 |
20130064442 | Determining Design Coordinates for Wafer Defects - Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects. | 03-14-2013 |
20130318485 | Design Alteration for Wafer Inspection - Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar. | 11-28-2013 |
20140037187 | Inspecting a Wafer and/or Predicting One or More Characteristics of a Device Being Formed on a Wafer - Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step. | 02-06-2014 |
20140153814 | Method and System for Mixed Mode Wafer Inspection - Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells. | 06-05-2014 |
20140199791 | Method and System for Universal Target Based Inspection and Metrology - Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool. | 07-17-2014 |