Patent application number | Description | Published |
20110050471 | Use of Three Phase Clock in Sigma Delta Modulator to Mitigate the Quantization Noise Folding - A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals. The modulated input signal is integrated using an integration capacitor to form an integrated value and the integrated value is compared to a threshold to form the one or more feedback signals. Parasitic capacitance of the one or more switches is initialized to an initial value prior to each intermittent coupling of the reference signal to the input signal using another non-overlapping clock signal. | 03-03-2011 |
20110199137 | LOOP FILTER AND VOLTAGE CONTROLLED OSCILLATOR FOR A PHASE-LOCKED LOOP - A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (g | 08-18-2011 |
20110267133 | CURRENT GENERATING CIRCUIT - A current generating circuit including a current mirror, an impedance device, a first voltage generating portion and a second voltage generating portion. The current mirror has a current output leg and a current generating leg. The impedance device is connected to the current generating leg. The first voltage generating portion can generate a first voltage that is complementary to absolute temperature. The second voltage generating portion can generate a second voltage that is proportional to absolute temperature. The first voltage generating portion and the second voltage generating portion are arranged to generate an impedance current across the impedance device. The current output leg is operable to output an output current based on the impedance current. The impedance device has an impedance value, a first terminal and a second terminal. An impedance voltage drop across the first terminal and the second terminal is equal to a product of the impedance value and the impedance current. The first voltage is based on an attenuation of the impedance voltage drop. | 11-03-2011 |
20120086510 | COMMON-MODE FEEDBACK AMPLIFIER - A circuit is provided for use with a reference voltage. The circuit includes a voltage source, a common-mode feedback amplifier and a feedback impedance portion. The common-mode feedback amplifier may be connected to the voltage source and may be arranged to receive the reference voltage. The common-mode feedback amplifier may include an input stage, an output stage, a positive input, a negative input and an output. The output may be connected to the feedback impedance portion. The feedback impedance portion may additionally be connected to one of the positive input and the negative input. A feedback factor, based on the feedback impedance portion, is less than one. | 04-12-2012 |
20120092050 | OSCILLATOR CIRCUIT AND METHOD FOR GAIN AND PHASE NOISE CONTROL - An oscillator circuit and method for gain and phase noise control. A gain and phase noise controlled oscillator circuit includes a variable electronic oscillator and a tuning loop circuit. In operation, the variable electronic oscillator generates a clock signal and has a clock signal frequency that is controlled by a sense voltage received by the variable electronic oscillator or by one or more capacitive loads coupled to the variable electronic oscillator. Further, the tuning loop circuit is coupled to the variable electronic oscillator and compares the sense voltage to a control voltage received by the tuning loop circuit and produces one or more correction signals based on the comparison, where the one or more capacitive loads change capacitance based on the one or more correction signals. | 04-19-2012 |
20120306678 | Three-level digital-to-analog converter - A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal. | 12-06-2012 |
20120319734 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A PHASED-LOCKED LOOP CIRCUIT - A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled. | 12-20-2012 |
20120319786 | AUTOCONFIGURABLE PHASE-LOCKED LOOP WHICH AUTOMATICALLY MAINTAINS A CONSTANT DAMPING FACTOR AND ADJUSTS THE LOOP BANDWIDTH TO A CONSTANT RATIO OF THE REFERENCE FREQUENCY - A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal. | 12-20-2012 |
20130241504 | SELF-CALIBRATING, STABLE LDO REGULATOR - A substantially unconditionally stable LOD regulator includes has first and second current paths. The first current path provides a reference current. The second current path receives an input voltage for developing a differential current with respect to the reference current based on the input voltage. The second current path has a sense resistor for sensing the differential current. A first current source biases the first and second current paths. A third current path senses the differential current and develops the input voltage in response thereto to control the differential current. A second current source biases the second current path. A first voltage follower circuit receives a first voltage on a first side of the sense resistor to provide an analog voltage output, and a second voltage follower circuit receives a second voltage on a second side of the sense resistor to provide a digital voltage output. | 09-19-2013 |
20140035768 | ANALOG-TO-DIGTAL CONVERTER - An analog-to-digital converter (ADC) comprises a plurality of time-interleaved integrating ADCs having feedback from an integrated output signal. In variations, the time-interleaved integrating ADCs have feedback compensation from at least one measure of quantization error. The time-interleaved integrating ADCs may also share a single comparator and may also share a single current source. | 02-06-2014 |