| Patent application number | Description | Published |
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| 20100032670 | ELECTRICAL TEST STRUCTURE TO DETECT STRESS INDUCED DEFECTS USING DIODES - A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects. | 02-11-2010 |
| 20100090340 | Drawn Dummy FeCAP, Via and Metal Structures - An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. | 04-15-2010 |
| 20110079878 | FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. | 04-07-2011 |
| 20110084323 | Transistor Performance Modification with Stressor Structures - A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries. | 04-14-2011 |
| 20120077287 | DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES - A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. | 03-29-2012 |
| 20120098071 | High Sheet Resistor in CMOS Flow - An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates. | 04-26-2012 |
| 20120241907 | FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. | 09-27-2012 |
| 20130065374 | Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching - A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch. | 03-14-2013 |
| 20140035061 | HIGH SHEET RESISTOR IN CMOS FLOW - An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates. | 02-06-2014 |
| 20140370621 | FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. | 12-18-2014 |
| 20150187655 | METHOD TO IMPROVE TRANSISTOR MATCHING - A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface. | 07-02-2015 |
| 20150187759 | HIGH SHEET RESISTOR IN CMOS FLOW - An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates. | 07-02-2015 |
| Patent application number | Description | Published |
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| 20080222647 | Method and system for load balancing of computing resources - A load balancing method incorporates temporarily inactive machines as part of the resources capable of executing tasks during heavy process requests periods to alleviate some of the processing load on other computing resources. This method determines which computing resources are available and prioritizes these resources for access by the load balancing process. A snap shot of the resource configuration and made secured along with all data on this system such that no contamination occurs between resident data on that machine and any data placed on that machine as put of the load balancing activities. After a predetermined period of time or a predetermined event, the availability of the temporary resources for load balancing activities ends. At this point, the original configuration and data is restored to the computing resource such that no trace of use of the resource in load balancing activities is detected to the user. | 09-11-2008 |
| 20090133026 | METHOD AND SYSTEM TO IDENTIFY CONFLICTS IN SCHEDULING DATA CENTER CHANGES TO ASSETS - An information technology services management product is provided with a change management component that identifies conflicts based on a wide range of information. When a change on a configuration item is scheduled, the change management component identifies, for example, affected business applications, affected service level agreements, resource availability, change schedule, workflow, resource dependencies, and the like. The change management component warns the user if a conflict is found. The user does not have to consult multiple sources of information and make a manual determination concerning conflicts. The change management component may also suggest a best time to schedule a change request based on the information available. The change management component provides a constrained interface such that the user cannot schedule a change request that violates any of the above requirements. The change management component also applies these requirements when changing an already scheduled change request. | 05-21-2009 |
| 20140052610 | SYSTEM AND METHOD FOR SOFTWARE ALLOCATION BASED ON FORECASTS AND CALENDARS - Systems and methods provide at least one software application to users from a software monitor computer server. The software application requires a license grant for use. The software monitor computer server tracks usage of the software application to develop historical use patterns. The software monitor computer server also receives calendar input from electronic calendars of the users and analyzing the calendar input to identify future calendared uses of the software application. This allows the software monitor computer server to predict the future license grant needs of the software application based on the historical use patterns and the future calendared uses of the software application. The software monitor computer server also provides substitute software applications to the users when an insufficient number of license grants are available to meet the future calendared uses of the software application. | 02-20-2014 |
| 20150347219 | Alerting Service Desk Users of Business Services Outages - An approach is provided in a service desk detects a current computer resource outage and identifies applications corresponding to the computer resource outage. The service desk uses historical service request entries to match the identified applications to users previously inquiring about the applications and, in turn, sends notifications to the users regarding the computer resource outage. | 12-03-2015 |
| Patent application number | Description | Published |
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| 20080263453 | METHOD AND APPARATUS FOR PROCESS CONFIGURATION - A computer implemented method, apparatus, and computer-usable program product for process configuration are provided in the illustrative embodiments. A process that is to be configured is identified. A list of tasks associated with the identified process is displayed. A set of the tasks displayed in the task list are selected. The selected tasks are configured according to one or more task parameters. If the process that is being configured is already running, the process is suspended before the selected tasks are configured. If the process is suspended, the process is resumed after the selected tasks have been configured. The process is identified, the list of task is displayed, and the one or more tasks are selected and configured using a graphical user interface. | 10-23-2008 |
| 20090099942 | Identification of Discrepancies in Actual and Expected Inventories in Computing Environment having Multiple Provisioning Orchestration Server Pool Boundaries - A system for establishing and maintaining inventories of computing environment assets comprising one or more custom collector interfaces that detect movement of assets from one environment to another, and an inventory scanner which modifies inventories for each environment based on monitored asset movements. The present invention is of especial benefit to autonomic and on-demand computing architectures. | 04-16-2009 |
| 20110214009 | Creation of Highly Available Pseudo-Clone Standby Servers for Rapid Failover Provisioning - Near clones for a set of targeted computing systems are provided by determining a highest common denominator set of components among the computing systems, producing a pseudo-clone configuration definition, and realizing one or more pseudo-clone computing systems as partially configured backups for the targeted computing systems. Upon a planned failover, actual failure, or quarantine action on a targeted computing system, a difference configuration is determined to complete the provisioning of the pseudo-clone system to serve as a replacement system for the failed or quarantined system. Failure predictions can be used to implement the pseudo-clone just prior to an expected first failure of any of the targeted systems. The system can also interface to an on-demand provisioning management system to effect automated workflows to realize pseudo-clones and replacement systems automatically, as needed. | 09-01-2011 |
| 20110214010 | Creation of Highly Available Pseudo-Clone Standby Servers for Rapid Failover Provisioning - Near clones for a set of targeted computing systems are provided by determining a highest common denominator set of components among the computing systems, producing a pseudo-clone configuration definition, and realizing one or more pseudo-clone computing systems as partially configured backups for the targeted computing systems. Upon a planned failover, actual failure, or quarantine action on a targeted computing system, a difference configuration is determined to complete the provisioning of the pseudo-clone system to serve as a replacement system for the failed or quarantined system. Failure predictions can be used to implement the pseudo-clone just prior to an expected first failure of any of the targeted systems. The system can also interface to an on-demand provisioning management system to effect automated workflows to realize pseudo-clones and replacement systems automatically, as needed. | 09-01-2011 |
| 20110289547 | TAKING CONFIGURATION MANAGEMENT DATA AND CHANGE BUSINESS PROCESS DATA INTO ACCOUNT WITH REGARD TO AUTHORIZATION AND AUTHENTICATION RULES - An approach receives a request from a user, typically a change implementer, on a computer system. The request includes a user identifier and a requested action. A current timestamp corresponding to a computer system clock is retrieved. Scheduled changes are retrieved from a data store accessible by the processor. The current timestamp is compared to the scheduled change periods. The requested action is allowed if the comparison reveals that the current timestamp is within one of the retrieved scheduled changes, and the requested action is denied if the comparison reveals that the current timestamp is outside of the retrieved scheduled change periods. | 11-24-2011 |
| 20130024720 | Creation of Highly Available Pseudo-Clone Standby Servers for Rapid Failover Provisioning - Near clones for a set of targeted computing systems are provided by determining a highest common denominator set of components among the computing systems, producing a pseudo-clone configuration definition, and realizing one or more pseudo-clone computing systems as partially configured backups for the targeted computing systems. Upon a planned failover, actual failure, or quarantine action on a targeted computing system, a difference configuration is determined to complete the provisioning of the pseudo-clone system to serve as a replacement system for the failed or quarantined system. Failure predictions can be used to implement the pseudo-clone just prior to an expected first failure of any of the targeted systems. The system can also interface to an on-demand provisioning management system to effect automated workflows to realize pseudo-clones and replacement systems automatically, as needed. | 01-24-2013 |
| 20130152164 | Taking Configuration Management Data and Change Business Process Data Into Account With Regard to Authorization and Authentication Rules - An approach receives a request from a user, typically a change implementer, on a computer system. The request includes a user identifier and a requested action. A current timestamp corresponding to a computer system clock is retrieved. Scheduled changes are retrieved from a data store accessible by the processor. The current timestamp is compared to the scheduled change periods. The requested action is allowed if the comparison reveals that the current timestamp is within one of the retrieved scheduled changes, and the requested action is denied if the comparison reveals that the current timestamp is outside of the retrieved scheduled change periods. | 06-13-2013 |
