Patent application number | Description | Published |
20080223287 | Plasma enhanced ALD process for copper alloy seed layers - A method of forming a copper alloy seed layer comprises providing a substrate in a reactor, performing a first ALD process to fabricate an alloy metal layer on the substrate, wherein the first ALD process uses an alloy metal precursor selected from a group of specific alloy metal precursors, performing a second ALD process to fabricate a copper metal layer on the alloy metal layer, wherein the second ALD process uses a copper metal precursor selected from a group of specific copper metal precursors, and annealing the alloy metal layer and the copper metal layer to form a graded Cu-alloy layer. | 09-18-2008 |
20080224235 | Selectively depositing aluminium in a replacement metal gate process - A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the reactor be less than or equal to 150° C., introducing methylpyrrolidine:alane (MPA) proximate to the surface of the barrier layer, and carrying out a CVD process to deposit aluminum metal on the barrier layer using a bottom-up deposition mechanism. | 09-18-2008 |
20080237861 | Novel Fluorine-Free Precursors and Methods for the Deposition of Conformal Conductive Films for Nanointerconnect Seed and Fill - A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor. | 10-02-2008 |
20080242880 | COPPER PRECURSORS FOR CVD/ALD/DIGITAL CVD OF COPPER METAL FILMS - Copper precursors useful for depositing copper or copper-containing films on substrates, e.g., microelectronic device substrates or other surfaces. The precursors includes copper compounds of various classes, including copper borohydrides, copper compounds with cyclopentadienyl-type ligands, copper compounds with cyclopentadienyl-type and isocyanide ligands, and stabilized copper hydrides. The precursors can be utilized in solid or liquid forms that are volatilized to form precursor vapor for contacting with the substrate, to form deposited copper by techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or rapid vapor deposition (digital CVD). | 10-02-2008 |
20090004385 | Copper precursors for deposition processes - In one embodiment, a method comprises providing a chemical phase deposition copper precursor within a chemical phase deposition chamber; and depositing a metal film onto a substrate with the copper precursor by a chemical phase deposition process. | 01-01-2009 |
20090004860 | ATOMIC LAYER VOLATILIZATION PROCESS FOR METAL LAYERS - A two-stage method to remove a metal layer from a substrate surface comprises using a CMP process to remove a first portion of the metal layer from the substrate surface, and using an ALV process to remove a second portion of the copper layer from the substrate surface. The ALV process comprises pulsing a co-reactant into a reactor housing the substrate, wherein the co-reactant reacts with the metal layer to form a volatile metal-containing product, and then evacuating the reactor to volatize and remove the metal-containing product. | 01-01-2009 |
20090022958 | AMORPHOUS METAL-METALLOID ALLOY BARRIER LAYER FOR IC DEVICES - A method for fabricating an amorphous metal-metalloid alloy layer for use in an IC device comprises providing a substrate in a reactor that includes a dielectric layer having a trench, pulsing a metal precursor into the reactor to deposit within the trench, wherein the metal precursor is selected from the group consisting of CpTa(CO) | 01-22-2009 |
20090160055 | IC solder reflow method and materials - Embodiments of IC manufacture resulting in improved electromigration and gap-fill performance of interconnect conductors are described in this application. Reflow agent materials such as Sn, Al, Mn, Mg, Ag, Au, Zn, Zr, and In may be deposited on an IC substrate, allowing PVD depositing of a Cu layer for gap-fill of interconnect channels in the IC substrate. The Cu layer, along with reflow agent layer, may then be reflowed into the interconnect channels, forming a Cu alloy with improved gap-fill and electromigration performance. Other embodiments are also described. | 06-25-2009 |
20090253270 | DEPOSITION METHOD FOR HIGH-K DIELECTRIC MATERIALS - A method for depositing a high-k dielectric material on a semiconductor substrate is disclosed. The method includes applying a chemical bath to a surface of a substrate, rinsing the surface, applying a co-reactant bath to the surface of the substrate, and rinsing the surface. The chemical bath includes a metal precursor which includes at least a hafnium compound, an aluminium compound, a titanium compound, zirconium compound, a scandium compound, a yttrium compound or a lanthanide compound. | 10-08-2009 |
20090315181 | Liquid phase molecular self-assembly for barrier deposition and structures formed thereby - Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise dissolving a metal precursor in a non-aqueous solvent in a bath; placing a substrate comprising an interconnect opening in the bath, wherein the metal precursor forms a monolayer within the interconnect opening; and placing the substrate in a coreactant mixture, wherein the coreactant reacts with the metal precursor to form a thin barrier monolayer. | 12-24-2009 |
20090321855 | Boundaries with elevated deuterium levels - A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium. | 12-31-2009 |
20090321934 | SELF-ALIGNED CAP AND BARRIER - A semiconductor device comprising an insulator layer formed on a substrate; a via formed by etching into the insulator layer to a first depth; a first metal layer formed over the insulator layer; a second metal layer deposited on the first metal layer to substantially fill the via; a metal-dopant alloy layer deposited over the second metal, wherein the dopant is diffused by annealing through the second metal layer and the first metal layer deposited in the via, such that the dopant migrates to a boundary between the first metal layer and the insulator to form a barrier; and an etch stop layer deposited over the via after planarization of the via and the insulator layer to form a barrier cap. | 12-31-2009 |
20100098960 | MAGNETIC INSULATOR NANOLAMINATE DEVICE FOR INTEGRATED SILICON VOLTAGE REGULATORS - A magnetic insulator nanolaminate device comprises a metal magnetic layer formed on a substrate, an insulating layer formed on the metal magnetic layer, wherein the insulating layer is formed by nitriding a portion of the metal magnetic layer, a chelating group layer formed on the insulating layer, and a metal seed layer bonded to the chelating group layer. The magnetic insulator nanolaminate device may be formed by depositing a metal layer on a substrate, converting a portion of the metal layer into an insulating layer using a nitridation process, and depositing a metal seed layer onto the insulating layer using a metal immobilization process, wherein the metal seed layer enables the deposition of a metal layer onto the insulating layer. | 04-22-2010 |
20100140717 | TUNABLE GATE ELECTRODE WORK FUNCTION MATERIAL FOR TRANSISTOR APPLICATIONS - Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film. | 06-10-2010 |
20100166981 | SURFACE CHARGE ENHANCED ATOMIC LAYER DEPOSITION OF PURE METALLIC FILMS - A method including applying an electric charge to a substrate in a chamber; introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including applying a removable electric charge to a substrate; in the presence of the applied electric charge, introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent with an externally applied electric charge. | 07-01-2010 |
20100200991 | Dopant Enhanced Interconnect - Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved. | 08-12-2010 |
20100230817 | Using Unstable Nitrides to Form Semiconductor Structures - Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place. | 09-16-2010 |
20100252929 | GROUP II ELEMENT ALLOYS FOR PROTECTING METAL INTERCONNECTS - A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect. | 10-07-2010 |
20100283570 | NANO-ENCAPSULATED MAGNETIC PARTICLE COMPOSITE LAYERS FOR INTEGRATED SILICON VOLTAGE REGULATORS - A method of forming an integrated silicon voltage regulator (ISVR) comprises providing a nano-encapsulated magnetic particle (NEMP) suspension, depositing a first layer of the NEMP suspension on an integrated circuit (IC) device, curing the first layer of the NEMP suspension to form a first NEMP composite layer, forming at least one inductor wire on the NEMP composite layer, depositing an interlayer dielectric material over the inductor wire, depositing a second layer of the NEMP suspension on the interlayer dielectric material, and curing the second layer of the NEMP suspension to form a second NEMP composite layer. | 11-11-2010 |
20110272811 | USING UNSTABLE NITRIDES TO FORM SEMICONDUCTOR STRUCTURES - Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place. | 11-10-2011 |
20120286372 | Reliability of high-K gate dielectric layers - A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability. | 11-15-2012 |