Patent application number | Description | Published |
20080212070 | KIT AND METHOD FOR MULTI-ANALYTE DETERMINATION - The invention is related to different embodiments of a kit for the simultaneous qualitative and/or quantitative determination of a multitude of analytes comprising
| 09-04-2008 |
20080299008 | Flow cell array and the utilization thereof for multianalyte determination - A one- or two-dimensional arrangement of flow cells is provided, as part of an array of sample compartments, with at least one inlet and outlet for each sample compartment, formed by a base plate and a body, with an arrangement of spatial recesses corresponding to the (geometrical) arrangement of the sample compartments, combined with the base plate. The arrangement allows for supplying to or removing from the sample compartments, which can be arranged at a high quantity on a small base area, even very small amounts of samples or reagents. An arrangement of one or more sample compartments includes a base plate and a body combined with the base plate in such a way that one or more recesses for generation of one or more flow cells fluidically sealed against one another, each with at least one inlet and one outlet, are formed between the base plate and the body, wherein at least one outlet of each flow cell is joined with a reservoir fluidically connected with the flow cell, the reservoir being operable to receive liquid exiting the flow cell, besides methods for its manufacturing and their use. | 12-04-2008 |
20100130370 | FLOW CELL ARRAY AND THE UTILIZATION THEREOF FOR MULTIANALYTE DETERMINATION - A one- or two-dimensional arrangement of flow cells is provided, as part of an array of sample compartments, with at least one inlet and outlet for each sample compartment, formed by a base plate and a body, with an arrangement of spatial recesses corresponding to the (geometrical) arrangement of the sample compartments, combined with the base plate. The arrangement allows for supplying to or removing from the sample compartments, which can be arranged at a high quantity on a small base area, even very small amounts of samples or reagents. An arrangement of one or more sample compartments includes a base plate and a body combined with the base plate in such a way that one or more recesses for generation of one or more flow cells fluidically sealed against one another, each with at least one inlet and one outlet, are formed between the base plate and the body, wherein at least one outlet of each flow cell is joined with a reservoir fluidically connected with the flow cell, the reservoir being operable to receive liquid exiting the flow cell, besides methods for its manufacturing and their use. | 05-27-2010 |
20100227773 | Device and method for determining multiple analytes - A device includes a planar optical waveguide, as part of a sensor platform, and, connected to the platform directly or by means of a sealing medium, a sealing layer. The sealing layer forms either directly or by means of a sealing medium a tightly sealing layer. The sealing layer includes a multitude of recesses at least open towards the sensor platform, which form a corresponding multitude of sample compartments in a 2-dimensional arrangement. Each of the sample compartments has different biological or biochemical recognition elements, for the specific recognition and binding of different analytes, immobilized in five or more discrete measurement areas, wherein the measurement areas are in optical interaction with excitation light emanating from the optical waveguide, as part of the sensor platform which forms a demarcation of the sample compartments, and wherein the sample compartments are operable to be cleared from received sample or reagent solutions and to then receive, optionally without washing steps, further sample or reagent solutions, which are supplied to the same sample compartments. | 09-09-2010 |
Patent application number | Description | Published |
20080212577 | CHIP CIRCUIT FOR COMBINED AND DATA COMPRESSED FIFO ARBITRATION FOR A NON-BLOCKING SWITCH - A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped. | 09-04-2008 |
20120159132 | Accelerating Data Packet Parsing - Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle. | 06-21-2012 |
20120300642 | Accelerating Data Packet Parsing - Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle. | 11-29-2012 |
20130311697 | SWITCHING DEVICE FOR ROUTING DATA, COMUTER INTERCONNECTION NETWORK AND ROUTING METHOD USING SUCH DEVICE - The invention is directed to a switching device (S | 11-21-2013 |
20160085722 | DATA PACKET PROCESSING - Proposed is an action machine for processing packet data in a network processor. The action machine comprises: first and second data storage units adapted to store data for processing; and a processing unit adapted to process data from the first and second data storage units. The first storage unit is adapted to be accessed by the processing unit and a unit external to the action machine, and the second storage unit is adapted to only be accessed by the processing unit. | 03-24-2016 |
20160105267 | ASSEMBLING RESPONSE PACKETS - Proposed is an action machine for assembling response packets in a network processor. The action machine comprises: a first register array adapted to store data for entry into fixed-length fields of differing response packets, a fixed-length field having the same length in the differing response packets; and a second register array adapted to store data for entry into variable-length fields of differing response packets, a variable-length field having different values or lengths in the differing response packets. The action machine is adapted to assemble a response packet by combining data stored in the first register array with data stored in the second register array. | 04-14-2016 |
20160134529 | NETWORK CONTROLLER-SIDEBAND INTERFACE PORT CONTROLLER - Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication. | 05-12-2016 |
20160134549 | STICKY AND TRANSIENT MARKERS FOR A PACKET PARSER - A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected. | 05-12-2016 |
20160134559 | NETWORK CONTROLLER-SIDEBAND INTERFACE PORT CONTROLLER - Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication. | 05-12-2016 |
Patent application number | Description | Published |
20120151307 | CHECKSUM VERIFICATION ACCELERATOR - Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum. | 06-14-2012 |
20120155267 | SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES - According to embodiments of the invention, there is provided a method, a system, and a computer program product for operating a network processor. The network processor processing a received data packet by reading a flow identification in the data packet; determining a quality of service criteria (QoSC) for the data packet; mapping the flow identification and the QoSC into an index for selecting a receive-queue for routing the data packet; and utilizing the index to route the data packet to the receive-queue. | 06-21-2012 |
20120218885 | SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES - According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue. | 08-30-2012 |
20120221928 | CHECKSUM VERIFICATION ACCELERATOR - Disclosed a method for validating a data packet by a network processor supporting a first, network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet: identities a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The method produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The method validates the data packet by comparing the data packet checksum to the second checksum. | 08-30-2012 |
20120300630 | IDENTIFICATION OF QOS CLASSIFICATION BASED ON PACKET ATTRIBUTES - A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet. | 11-29-2012 |