Patent application number | Description | Published |
20140164880 | ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY - An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold. | 06-12-2014 |
20140281767 | RECOVERY STRATEGY THAT REDUCES ERRORS MISIDENTIFIED AS RELIABLE - A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window. | 09-18-2014 |
20150077277 | REDUCED POLAR CODES - A method for encoding a reduced polar code is disclosed. The method generally includes steps (A) to (C). Step (A) may generate the intermediate codeword by polar code encoding input data. Step (B) may remove one or more bits from one of (i) a first part of the intermediate codeword and (ii) a second part of the intermediate codeword. Step (C) may generate an output codeword by concatenating the first part of the intermediate codeword with the second part of the intermediate codeword after the bits are removed. | 03-19-2015 |
20150128006 | DEVICE QUALITY METRICS USING UNSATISFIED PARITY CHECKS - An apparatus having a device and a circuit is disclosed. The device is configured to convey a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword, (iii) generate a value by counting a number of unsatisfied parity checks in the syndrome and (iv) generate a quality metric of the device according to the value. | 05-07-2015 |
20150149855 | BIT-LINE DEFECT DETECTION USING UNSATISIFIED PARITY CODE CHECKS - An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines. | 05-28-2015 |
20150162057 | MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY - An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads. | 06-11-2015 |
20150229337 | MITIGATION OF WRITE ERRORS IN MULTI-LEVEL CELL FLASH MEMORY THROUGH ADAPTIVE ERROR CORRECTION CODE DECODING - An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process. | 08-13-2015 |
20150236715 | REDUCED POLAR CODES - A method for encoding a reduced polar code is disclosed. The method generally includes (a) modifying an input codeword including polar code encoded input data by removing one or more bits from one of (i) a first part of the input codeword and (ii) a second part of the input codeword and (b) generating an output codeword by concatenating the first and the second parts of the modified input codeword. | 08-20-2015 |
20150243363 | ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES - An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values. | 08-27-2015 |